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/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
[all …]
/kernel/linux/linux-6.6/drivers/clk/ralink/
Dclk-mt7621.c71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
80 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
82 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
[all …]
/kernel/linux/linux-6.6/drivers/clk/uniphier/
Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dmediatek,mt7621-sysc.yaml78 "50m", "125m", "150m",
79 "250m", "270m";
/kernel/linux/linux-6.6/Documentation/arch/arm/omap/
Ddss.rst167 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
201 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
325 "1:4M" to allocate 4M for fb1.
343 3 - 270 degree rotation
/kernel/linux/linux-5.10/Documentation/arm/omap/
Ddss.rst167 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
201 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
325 "1:4M" to allocate 4M for fb1.
343 3 - 270 degree rotation
/kernel/linux/linux-6.6/Documentation/hwmon/
Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
71 i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
72 i5 3427U, 3360M/3320M 105
83 i7 660UM/640/620, 640LM/620, 620M, 610E 105
84 i5 540UM/520/430, 540M/520/450/430 105
85 i3 330E, 370M/350/330 90 rPGA, 105 BGA
124 N280/270 90
/kernel/linux/linux-5.10/Documentation/hwmon/
Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
71 i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
72 i5 3427U, 3360M/3320M 105
83 i7 660UM/640/620, 640LM/620, 620M, 610E 105
84 i5 540UM/520/430, 540M/520/450/430 105
85 i3 330E, 370M/350/330 90 rPGA, 105 BGA
124 N280/270 90
/kernel/linux/linux-6.6/Documentation/fb/
Dmodedb.rst23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
31 - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
32 - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
35 - PAL-M: 480i output, with the CCIR System-M TV mode and PAL color encoding
37 If 'M' is specified in the mode_option argument (after <yres> and before
41 If 'i' is specified, calculate for an interlaced mode. And if 'm' is
45 Sample usage: 1024x768M@60m - CVT timing with margins
75 degrees. Valid values are 0, 90, 180 and 270.
77 "PAL-M", "PAL-N", or "SECAM".
125 <pix>M<a>[-R]
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dmodedb.rst23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
29 If 'M' is specified in the mode_option argument (after <yres> and before
33 If 'i' is specified, calculate for an interlaced mode. And if 'm' is
37 Sample usage: 1024x768M@60m - CVT timing with margins
67 degrees. Valid values are 0, 90, 180 and 270.
115 <pix>M<a>[-R]
118 M = always present
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
Dcrg-hi3798cv200.c48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
55 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
56 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
58 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
[all …]
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dcrg-hi3798cv200.c48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
55 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
56 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
58 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8192u/ieee80211/
Drtl819x_HTProc.c24 { {27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540,
26 12, 162, 216, 270, 243, 324, 405, 216, 270, 270, 324, 378, 378, 432, 324, 405,
27 405, 486, 567, 567, 648, 270, 324, 378, 324, 378, 432, 486, 432, 486, 540, 540,
29 {30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600,
30 90, 180, 270, 360, 540, 720, 810, 900, 120, 240, 360, 480, 720, 960, 1080, 1200,
31 13, 180, 240, 300, 270, 360, 450, 240, 300, 300, 360, 420, 420, 480, 360, 450,
142 …IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 20M = %s\n", (pCapELE->ShortGI20Mhz) ? "… in HTDebugHTCapability()
143 …IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 40M = %s\n", (pCapELE->ShortGI40Mhz) ? "… in HTDebugHTCapability()
1267 //if in half N mode, set to 20M bandwidth please 09.08.2008 WB. in HTSetConnectBwMode()
/kernel/linux/linux-5.10/drivers/staging/rtl8192u/ieee80211/
Drtl819x_HTProc.c24 { {27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540,
26 12, 162, 216, 270, 243, 324, 405, 216, 270, 270, 324, 378, 378, 432, 324, 405,
27 405, 486, 567, 567, 648, 270, 324, 378, 324, 378, 432, 486, 432, 486, 540, 540,
29 {30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600,
30 90, 180, 270, 360, 540, 720, 810, 900, 120, 240, 360, 480, 720, 960, 1080, 1200,
31 13, 180, 240, 300, 270, 360, 450, 240, 300, 300, 360, 420, 420, 480, 360, 450,
142 …IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 20M = %s\n", (pCapELE->ShortGI20Mhz) ? "… in HTDebugHTCapability()
143 …IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 40M = %s\n", (pCapELE->ShortGI40Mhz) ? "… in HTDebugHTCapability()
1270 //if in half N mode, set to 20M bandwidth please 09.08.2008 WB. in HTSetConnectBwMode()
/kernel/linux/linux-5.10/drivers/staging/fbtft/
Dfb_ili9163.c8 * .S.U.M.O.T.O.Y. by Max MC Costa (https://github.com/sumotoy/TFT_ILI9163C).
130 case 270: in set_addr_win()
174 case 270: in set_var()
/kernel/linux/linux-6.6/drivers/staging/fbtft/
Dfb_ili9163.c8 * .S.U.M.O.T.O.Y. by Max MC Costa (https://github.com/sumotoy/TFT_ILI9163C).
130 case 270: in set_addr_win()
174 case 270: in set_var()
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Ds5h1411.c143 { 0x387, 270, },
186 { 0x14b5, 270, },
315 { 0x53a0, 270, },
475 enum fe_modulation m) in s5h1411_enable_modulation() argument
479 dprintk("%s(0x%08x)\n", __func__, m); in s5h1411_enable_modulation()
481 if ((state->first_tune == 0) && (m == state->current_modulation)) { in s5h1411_enable_modulation()
487 switch (m) { in s5h1411_enable_modulation()
510 state->current_modulation = m; in s5h1411_enable_modulation()
Ds5h1409.c116 { 896, 270, },
160 { 22, 270, },
286 { 92, 270, },
391 enum fe_modulation m) in s5h1409_enable_modulation() argument
395 dprintk("%s(0x%08x)\n", __func__, m); in s5h1409_enable_modulation()
397 switch (m) { in s5h1409_enable_modulation()
418 state->current_modulation = m; in s5h1409_enable_modulation()
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Ds5h1411.c143 { 0x387, 270, },
186 { 0x14b5, 270, },
315 { 0x53a0, 270, },
475 enum fe_modulation m) in s5h1411_enable_modulation() argument
479 dprintk("%s(0x%08x)\n", __func__, m); in s5h1411_enable_modulation()
481 if ((state->first_tune == 0) && (m == state->current_modulation)) { in s5h1411_enable_modulation()
487 switch (m) { in s5h1411_enable_modulation()
510 state->current_modulation = m; in s5h1411_enable_modulation()
Ds5h1409.c116 { 896, 270, },
160 { 22, 270, },
286 { 92, 270, },
391 enum fe_modulation m) in s5h1409_enable_modulation() argument
395 dprintk("%s(0x%08x)\n", __func__, m); in s5h1409_enable_modulation()
397 switch (m) { in s5h1409_enable_modulation()
418 state->current_modulation = m; in s5h1409_enable_modulation()
/kernel/linux/linux-6.6/arch/mips/boot/dts/ralink/
Dmt7621.dtsi69 "50m", "125m", "150m",
70 "250m", "270m";
/kernel/linux/linux-5.10/include/uapi/linux/
Dif_arp.h12 * Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source.
53 #define ARPHRD_ROSE 270
/kernel/linux/linux-6.6/include/uapi/linux/
Dif_arp.h12 * Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source.
53 #define ARPHRD_ROSE 270
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z16/
Dextended.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
24 "Unit": "CPU-M-CF",
31 "Unit": "CPU-M-CF",
38 "Unit": "CPU-M-CF",
45 "Unit": "CPU-M-CF",
52 "Unit": "CPU-M-CF",
59 "Unit": "CPU-M-CF",
66 "Unit": "CPU-M-CF",
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-pll.c163 /* Maximum lock time can be 270 * PDIV cycles */
164 #define PLL35XX_LOCK_FACTOR (270)
935 u32 r, p, m, s, pll_stat; in samsung_pll2550x_recalc_rate() local
943 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; in samsung_pll2550x_recalc_rate()
946 fvco *= m; in samsung_pll2550x_recalc_rate()
960 /* Maximum lock time can be 270 * PDIV cycles */
961 #define PLL2550XX_LOCK_FACTOR 270

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