Home
last modified time | relevance | path

Searched +full:5 +full:p49v5923 (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Didt,versaclock5.yaml7 title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
16 - 5P49V5923:
21 - 5P49V5933:
39 - idt,5p49v5923
40 - idt,5p49v5925
41 - idt,5p49v5933
42 - idt,5p49v5935
43 - idt,5p49v6901
44 - idt,5p49v6965
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Didt,versaclock5.yaml7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
16 - 5P49V5923:
21 - 5P49V5933:
53 - idt,5p49v5923
54 - idt,5p49v5925
55 - idt,5p49v5933
56 - idt,5p49v5935
57 - idt,5p49v60
58 - idt,5p49v6901
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/renesas/
Dsalvator-x.dtsi23 compatible = "idt,5p49v5923";
Dhihope-common.dtsi196 compatible = "idt,5p49v5923";
329 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dsalvator-x.dtsi23 compatible = "idt,5p49v5923";
Dhihope-common.dtsi188 compatible = "idt,5p49v5923";
321 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
/kernel/linux/linux-5.10/drivers/clk/
Dclk-versaclock5.c3 * Driver for IDT Versaclock 5
96 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
124 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
135 #define VC5_MAX_CLK_OUT_NUM 5
420 u8 fb[5]; in vc5_pll_recalc_rate()
422 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_recalc_rate()
464 u8 fb[5]; in vc5_pll_set_rate()
472 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_set_rate()
1126 .clk_out_cnt = 5,
1140 .clk_out_cnt = 5,
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-versaclock5.c3 * Driver for IDT Versaclock 5
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
133 #define VC5_MAX_CLK_OUT_NUM 5
436 u8 fb[5]; in vc5_pll_recalc_rate()
438 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_recalc_rate()
478 u8 fb[5]; in vc5_pll_set_rate()
486 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_set_rate()
820 * After getting feedback from Renesas, the .5pF steps were the in vc5_map_cap_value()
828 * The Programmer's guide shows XTAL[5:0] but in reality, in vc5_map_cap_value()
[all …]