| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rv770_dpm.c | 49 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
56 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
63 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
80 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
150 if (rdev->family == CHIP_RV770) in rv770_mg_clock_gating_enable()
158 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
229 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ? in rv770_get_seq_value()
240 pi->soft_regs_start + reg_offset,
241 value, pi->sram_end);
251 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
[all …]
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| D | rv740_dpm.c | 125 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
126 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
127 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
128 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
129 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
131 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
158 if (pi->sclk_ss) { in rv740_populate_sclk_value()
176 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
[all …]
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| D | radeon_mode.h | 41 #include <linux/i2c-algo-bit.h>
98 /* radeon gpio-based i2c
120 /* uses multi-media i2c engine */
249 /* DVI-I properties */
430 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
610 u32 clkf : 12; member
612 u32 clkf : 12;
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| D | cypress_dpm.c | 60 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
77 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
103 if (pi->gfx_clock_gating) {
126 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
151 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
181 if (rdev->family == CHIP_CEDAR) in cypress_mg_clock_gating_enable()
183 else if (rdev->family == CHIP_REDWOOD) in cypress_mg_clock_gating_enable()
195 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
198 if (eg_pi->mcls) { in cypress_mg_clock_gating_enable()
216 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
[all …]
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| D | rv770d.h | 119 #define CLKF(x) ((x) << 0) macro
701 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
706 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
863 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
868 #define HDMI_OFFSET0 (0x7400 - 0x7400)
869 #define HDMI_OFFSET1 (0x7800 - 0x7400)
880 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (def…
882 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
883 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
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| D | nid.h | 561 #define CLKF(x) ((x) << 0) macro
1196 /* 0 - always
1197 * 1 - <
1198 * 2 - <=
1199 * 3 - ==
1200 * 4 - !=
1201 * 5 - >=
1202 * 6 - >
1205 /* 0 - reg
1206 * 1 - mem
[all …]
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| D | ni_dpm.c | 729 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
736 struct ni_ps *ps = rps->ps_priv; in ni_get_ps()
752 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000), in ni_calculate_leakage_for_v_and_t_formula()
753 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature))); in ni_calculate_leakage_for_v_and_t_formula()
754 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000), in ni_calculate_leakage_for_v_and_t_formula()
755 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc))); in ni_calculate_leakage_for_v_and_t_formula()
776 /* we never hit the non-gddr5 limit so disable it */ in ni_dpm_vblank_too_short()
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; in ni_dpm_vblank_too_short()
796 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
802 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
[all …]
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| D | sid.h | 620 #define CLKF(x) ((x) << 16) macro
716 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (defaul…
718 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
719 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
910 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
1638 /* 0 - register
1639 * 1 - memory (sync - via GRBM)
1640 * 2 - tc/l2
1641 * 3 - gds
1642 * 4 - reserved
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | rv770_dpm.c | 51 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
82 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
152 if (rdev->family == CHIP_RV770) in rv770_mg_clock_gating_enable()
160 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
231 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ? in rv770_get_seq_value()
242 pi->soft_regs_start + reg_offset,
243 value, pi->sram_end);
253 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
[all …]
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| D | rv740_dpm.c | 124 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; in rv740_populate_sclk_value()
125 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv740_populate_sclk_value()
126 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv740_populate_sclk_value()
127 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv740_populate_sclk_value()
128 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv740_populate_sclk_value()
130 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
157 if (pi->sclk_ss) { in rv740_populate_sclk_value()
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
[all …]
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| D | radeon_mode.h | 40 #include <linux/i2c-algo-bit.h>
97 /* radeon gpio-based i2c
119 /* uses multi-media i2c engine */
246 /* DVI-I properties */
421 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
573 u32 clkf : 12; member
575 u32 clkf : 12;
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| D | cypress_dpm.c | 58 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
75 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
101 if (pi->gfx_clock_gating) {
124 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
149 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
179 if (rdev->family == CHIP_CEDAR) in cypress_mg_clock_gating_enable()
181 else if (rdev->family == CHIP_REDWOOD) in cypress_mg_clock_gating_enable()
193 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
196 if (eg_pi->mcls) { in cypress_mg_clock_gating_enable()
214 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
[all …]
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| D | rv770d.h | 119 #define CLKF(x) ((x) << 0) macro
701 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
706 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
863 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */
868 #define HDMI_OFFSET0 (0x7400 - 0x7400)
869 #define HDMI_OFFSET1 (0x7800 - 0x7400)
880 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (def…
882 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
883 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
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| D | nid.h | 561 #define CLKF(x) ((x) << 0) macro
1196 /* 0 - always
1197 * 1 - <
1198 * 2 - <=
1199 * 3 - ==
1200 * 4 - !=
1201 * 5 - >=
1202 * 6 - >
1205 /* 0 - reg
1206 * 1 - mem
[all …]
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| D | ni_dpm.c | 728 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps()
751 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000), in ni_calculate_leakage_for_v_and_t_formula()
752 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature))); in ni_calculate_leakage_for_v_and_t_formula()
753 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000), in ni_calculate_leakage_for_v_and_t_formula()
754 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc))); in ni_calculate_leakage_for_v_and_t_formula()
775 /* we never hit the non-gddr5 limit so disable it */ in ni_dpm_vblank_too_short()
776 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; in ni_dpm_vblank_too_short()
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
801 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
[all …]
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| D | sid.h | 620 #define CLKF(x) ((x) << 16) macro
716 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (defaul…
718 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
719 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
910 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
1638 /* 0 - register
1639 * 1 - memory (sync - via GRBM)
1640 * 2 - tc/l2
1641 * 3 - gds
1642 * 4 - reserved
[all …]
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| D | cikd.h | 743 #define CLKF(x) ((x) << 16) macro
983 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
990 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
993 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
998 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
1729 /* 0 - register
1730 * 1 - memory (sync - via GRBM)
1731 * 2 - gl2
1732 * 3 - gds
1733 * 4 - reserved
[all …]
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| /kernel/linux/linux-6.6/arch/mips/include/asm/octeon/ |
| D | cvmx-lmcx-defs.h | 7 * Copyright (c) 2003-2012 Cavium Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1379 uint64_t clkf:7; member
1381 uint64_t clkf:7;
2124 uint64_t clkf:12; member
2142 uint64_t clkf:12;
2156 uint64_t clkf:12; member
2174 uint64_t clkf:12;
2186 uint64_t clkf:12; member
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-lmcx-defs.h | 7 * Copyright (c) 2003-2012 Cavium Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1379 uint64_t clkf:7; member
1381 uint64_t clkf:7;
2124 uint64_t clkf:12; member
2142 uint64_t clkf:12;
2156 uint64_t clkf:12; member
2174 uint64_t clkf:12;
2186 uint64_t clkf:12; member
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
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| /kernel/linux/linux-5.10/drivers/crypto/cavium/nitrox/ |
| D | nitrox_csr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226 * struct aqm_grp_execmsk_lo - Available AE engines for the group
243 * struct aqm_grp_execmsk_hi - Available AE engines for the group
260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337 * struct aqmq_en - AQM Queue Enable Registers
[all …]
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| /kernel/linux/linux-6.6/drivers/crypto/cavium/nitrox/ |
| D | nitrox_csr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226 * struct aqm_grp_execmsk_lo - Available AE engines for the group
243 * struct aqm_grp_execmsk_hi - Available AE engines for the group
260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337 * struct aqmq_en - AQM Queue Enable Registers
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
35 #include "atom-bits.h"
52 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
53 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
54 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
55 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
56 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
57 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
58 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
59 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
35 #include "atom-bits.h"
52 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
53 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
54 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
55 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
56 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
57 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
58 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
59 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); in amdgpu_atombios_get_bus_rec_for_i2c_gpio()
[all …]
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