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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Dmediatek,mdp3-wrot.yaml82 clocks = <&mmsys CLK_MM_MDP_WROT0>;
Dmediatek-mdp.txt84 clocks = <&mmsys CLK_MM_MDP_WROT0>;
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt6765-mm.c37 GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
Dclk-mt6797-mm.c57 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
Dclk-mt8183-mm.c53 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
Dclk-mt6779-mm.c52 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
Dclk-mt8173-mm.c59 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
Dclk-mt2712-mm.c74 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
/kernel/linux/linux-6.6/drivers/clk/mediatek/
Dclk-mt6765-mm.c31 GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
Dclk-mt6797-mm.c45 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
Dclk-mt8183-mm.c53 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
Dclk-mt6795-mm.c45 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
Dclk-mt6779-mm.c53 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
Dclk-mt8173-mm.c48 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
Dclk-mt2712-mm.c56 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmediatek-mdp.txt90 clocks = <&mmsys CLK_MM_MDP_WROT0>;
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dmediatek,mt6795-clk.h231 #define CLK_MM_MDP_WROT0 12 macro
Dmt6797-clk.h227 #define CLK_MM_MDP_WROT0 13 macro
Dmt6765-clk.h256 #define CLK_MM_MDP_WROT0 5 macro
Dmt8173-clk.h259 #define CLK_MM_MDP_WROT0 12 macro
Dmt2712-clk.h313 #define CLK_MM_MDP_WROT0 12 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dmt6797-clk.h227 #define CLK_MM_MDP_WROT0 13 macro
Dmt8173-clk.h260 #define CLK_MM_MDP_WROT0 12 macro
Dmt6765-clk.h256 #define CLK_MM_MDP_WROT0 5 macro
Dmt2712-clk.h313 #define CLK_MM_MDP_WROT0 12 macro

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