| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | fiq.c | 3 * linux/arch/arm/kernel/fiq.c
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
10 * FIQ support re-written by Russell King to be more generic
12 * We now properly support a method by which the FIQ handlers can
14 * the FIQ vector itself.
17 * 1. Owner A claims FIQ:
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
[all …]
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| D | fiqasm.S | 4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
12 * FIQ support re-written by Russell King to be more generic
21 * Taking an interrupt in FIQ mode is death, so both these functions
28 msr cpsr_c, r2 @ select FIQ mode
41 msr cpsr_c, r2 @ select FIQ mode
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | fiq.c | 3 * linux/arch/arm/kernel/fiq.c
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
10 * FIQ support re-written by Russell King to be more generic
12 * We now properly support a method by which the FIQ handlers can
14 * the FIQ vector itself.
17 * 1. Owner A claims FIQ:
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
[all …]
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| D | fiqasm.S | 4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
12 * FIQ support re-written by Russell King to be more generic
21 * Taking an interrupt in FIQ mode is death, so both these functions
28 msr cpsr_c, r2 @ select FIQ mode
41 msr cpsr_c, r2 @ select FIQ mode
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| /kernel/linux/linux-5.10/fs/fuse/ |
| D | dev.c | 195 u64 fuse_get_unique(struct fuse_iqueue *fiq) in fuse_get_unique() argument
197 fiq->reqctr += FUSE_REQ_ID_STEP; in fuse_get_unique()
198 return fiq->reqctr; in fuse_get_unique()
208 * A new request is available, wake fiq->waitq
210 static void fuse_dev_wake_and_unlock(struct fuse_iqueue *fiq) in fuse_dev_wake_and_unlock() argument
211 __releases(fiq->lock) in fuse_dev_wake_and_unlock()
213 wake_up(&fiq->waitq); in fuse_dev_wake_and_unlock()
214 kill_fasync(&fiq->fasync, SIGIO, POLL_IN); in fuse_dev_wake_and_unlock()
215 spin_unlock(&fiq->lock); in fuse_dev_wake_and_unlock()
225 static void queue_request_and_unlock(struct fuse_iqueue *fiq, in queue_request_and_unlock() argument
[all …]
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| /kernel/linux/linux-6.6/fs/fuse/ |
| D | dev.c | 195 u64 fuse_get_unique(struct fuse_iqueue *fiq) in fuse_get_unique() argument
197 fiq->reqctr += FUSE_REQ_ID_STEP; in fuse_get_unique()
198 return fiq->reqctr; in fuse_get_unique()
208 * A new request is available, wake fiq->waitq
210 static void fuse_dev_wake_and_unlock(struct fuse_iqueue *fiq) in fuse_dev_wake_and_unlock() argument
211 __releases(fiq->lock) in fuse_dev_wake_and_unlock()
213 wake_up(&fiq->waitq); in fuse_dev_wake_and_unlock()
214 kill_fasync(&fiq->fasync, SIGIO, POLL_IN); in fuse_dev_wake_and_unlock()
215 spin_unlock(&fiq->lock); in fuse_dev_wake_and_unlock()
225 static void queue_request_and_unlock(struct fuse_iqueue *fiq, in queue_request_and_unlock() argument
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| D | ams-delta-fiq.c | 3 * Amstrad E3 FIQ handling
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
25 #include "ams-delta-fiq.h"
29 .name = "ams-delta-fiq"
33 * This buffer is shared between FIQ and IRQ contexts.
34 * The FIQ and IRQ isrs can both read and write it.
36 * followed by the circular buffer where the FIQ isr stores
38 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
58 * until the IRQ counter catches the FIQ incremented interrupt counter. in deferred_fiq()
[all …]
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| D | ams-delta-fiq-handler.S | 3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
14 #include <linux/platform_data/ams-delta-fiq.h>
20 #include "ams-delta-fiq.h"
92 @ FIQ intrrupt handler
99 beq exit @ none - spurious FIQ? exit
103 mov r8, #2 @ reset FIQ agreement
113 subs pc, lr, #4 @ return from FIQ
137 @ Keyboard clock FIQ mode interrupt handler
221 @ Hook switch interrupt FIQ mode simple handler
238 @ Modem FIQ mode interrupt handler stub
[all …]
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| D | irq.c | 98 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
99 * mailing list threads on FIQ handlers if you are planning to
100 * add a FIQ handler for OMAP.
102 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) in omap_irq_set_cfg() argument
108 /* FIQ is only available on bank 0 interrupts */ in omap_irq_set_cfg()
109 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
110 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); in omap_irq_set_cfg()
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| D | ams-delta-fiq.h | 4 * arch/arm/mach-omap1/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h
22 * Interrupt number used for passing control from FIQ to IRQ.
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| /kernel/linux/linux-6.6/arch/arm/mach-omap1/ |
| D | ams-delta-fiq.c | 3 * Amstrad E3 FIQ handling
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
27 #include "ams-delta-fiq.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
36 * The FIQ and IRQ isrs can both read and write it.
38 * followed by the circular buffer where the FIQ isr stores
40 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
60 * until the IRQ counter catches the FIQ incremented interrupt counter. in deferred_fiq()
[all …]
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| D | ams-delta-fiq-handler.S | 3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
14 #include <linux/platform_data/ams-delta-fiq.h>
22 #include "ams-delta-fiq.h"
93 @ FIQ intrrupt handler
100 beq exit @ none - spurious FIQ? exit
104 mov r8, #2 @ reset FIQ agreement
114 subs pc, lr, #4 @ return from FIQ
138 @ Keyboard clock FIQ mode interrupt handler
222 @ Hook switch interrupt FIQ mode simple handler
239 @ Modem FIQ mode interrupt handler stub
[all …]
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| D | irq.c | 97 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
98 * mailing list threads on FIQ handlers if you are planning to
99 * add a FIQ handler for OMAP.
101 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) in omap_irq_set_cfg() argument
107 /* FIQ is only available on bank 0 interrupts */ in omap_irq_set_cfg()
108 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
109 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); in omap_irq_set_cfg()
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| D | ams-delta-fiq.h | 4 * arch/arm/mach-omap1/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h
22 * Interrupt number used for passing control from FIQ to IRQ.
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-s3c24xx.c | 22 #include <linux/spi/s3c24xx-fiq.h>
25 #include <asm/fiq.h>
212 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
215 * used by the FIQ core to move data between main memory and the peripheral
221 * struct spi_fiq_code - FIQ code and header
224 * @data: The code itself to install as a FIQ handler.
233 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
236 * Claim the FIQ handler (only one can be active at any one time) and
241 * as normal, since the IRQ will have been re-routed to the FIQ handler.
252 /* try and claim fiq if we haven't got it, and if not in s3c24xx_spi_tryfiq()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | fiq.h | 3 * arch/arm/include/asm/fiq.h
5 * Support for FIQ on ARM architectures.
9 * NOTE: The FIQ mode registers are not magically preserved across
28 * reacquire FIQ
40 extern void enable_fiq(int fiq);
41 extern void disable_fiq(int fiq);
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| D | ecard.h | 104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
147 void __iomem *fiqaddr; /* address of FIQ register */
149 unsigned char fiqmask; /* FIQ mask */
154 void *fiq_data; /* Data for use for FIQ by card */
160 CONST unsigned int fiq; /* FIQ number (for request_irq) */ member
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| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| D | fiq.h | 3 * arch/arm/include/asm/fiq.h
5 * Support for FIQ on ARM architectures.
9 * NOTE: The FIQ mode registers are not magically preserved across
28 * reacquire FIQ
40 extern void enable_fiq(int fiq);
41 extern void disable_fiq(int fiq);
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| D | ecard.h | 104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
147 void __iomem *fiqaddr; /* address of FIQ register */
149 unsigned char fiqmask; /* FIQ mask */
154 void *fiq_data; /* Data for use for FIQ by card */
160 CONST unsigned int fiq; /* FIQ number (for request_irq) */ member
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | apple,aic2.yaml | 27 This device also represents the FIQ interrupt sources on platforms using AIC,
29 FIQ-based Fast IPIs.
47 - 1: FIQ
79 FIQ affinity can be expressed as a single "affinities" node,
80 containing a set of sub-nodes, one per FIQ with a non-default
87 apple,fiq-index:
89 The interrupt number specified as a FIQ, and for which
101 - apple,fiq-index
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| D | apple,aic.yaml | 31 This device also represents the FIQ interrupt sources on platforms using AIC,
50 - 1: FIQ
77 FIQ affinity can be expressed as a single "affinities" node,
78 containing a set of sub-nodes, one per FIQ with a non-default
85 apple,fiq-index:
87 The interrupt number specified as a FIQ, and for which
98 - apple,fiq-index
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-apple-aic.c | 36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
39 * - <1 nr flags> - FIQ #nr
163 * IMP-DEF sysregs that control FIQ sources
182 /* Guest timer FIQ enable register */
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
453 * FIQ irqchip
522 * the FIQ source state without having to peek down into sources... in aic_handle_fiq()
531 * Since not dealing with any of these results in a FIQ storm, in aic_handle_fiq()
580 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
592 .name = "AIC-FIQ",
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/mm/ |
| D | trans_pgd-asm.S | 43 invalid_vector hyp_stub_el2t_fiq_invalid // FIQ EL2t
48 invalid_vector hyp_stub_el2h_fiq_invalid // FIQ EL2h
53 invalid_vector hyp_stub_el1_fiq_invalid // FIQ 64-bit EL1
58 invalid_vector hyp_stub_32b_el1_fiq_invalid // FIQ 32-bit EL1
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| /kernel/linux/linux-6.6/include/linux/irqchip/ |
| D | irq-bcm2836.h | 13 * next 2 bits identify the CPU that the GPU FIQ goes to.
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
37 /* Same status bits as above, but for FIQ. */
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| /kernel/linux/linux-5.10/include/linux/irqchip/ |
| D | irq-bcm2836.h | 13 * next 2 bits identify the CPU that the GPU FIQ goes to.
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
37 /* Same status bits as above, but for FIQ. */
|