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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/imx/
DKconfig7 tristate "Freescale i.MX8QM LVDS display bridge"
14 Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
27 tristate "Freescale i.MX8QM/QXP pixel combiner"
33 Freescale i.MX8qm/qxp processors.
36 tristate "Freescale i.MX8QM/QXP display pixel link"
42 Freescale i.MX8qm/qxp processors.
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-ldb.yaml7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
Dfsl,imx8qxp-pixel-link.yaml7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
Dfsl,imx8qxp-pixel-combiner.yaml7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
/kernel/linux/linux-6.6/drivers/firmware/imx/
DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
20 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
Dimx-scu-soc.c85 return "i.MX8QM"; in imx_scu_soc_name()
/kernel/linux/linux-5.10/drivers/firmware/imx/
DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
20 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml7 title: Freescale i.MX8qm/qxp Control and Status Registers Module
13 As a system controller, the Freescale i.MX8qm/qxp Control and Status
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
110 # Device node example for i.MX8QM platform:
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml24 Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
28 The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
/kernel/linux/linux-6.6/drivers/phy/freescale/
DKconfig18 on NXP's i.MX8qm SoC.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-fsl-ftm.txt22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dpwm-fsl-ftm.txt22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8qm-mek.dts12 model = "Freescale i.MX8QM MEK";
/kernel/linux/linux-6.6/drivers/net/can/flexcan/
Dflexcan.h30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
/kernel/linux/linux-6.6/drivers/media/platform/nxp/imx-jpeg/
Dmxc-jpeg.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.h3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/kernel/linux/linux-6.6/drivers/pinctrl/freescale/
Dpinctrl-imx8qm.c333 MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
/kernel/linux/linux-5.10/drivers/pinctrl/freescale/
Dpinctrl-imx8qm.c333 MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_mqs.c191 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
/kernel/linux/linux-6.6/drivers/remoteproc/
Dimx_dsp_rproc.c279 /* Specific configuration for i.MX8QM */
951 * On i.MX8QM and i.MX8QXP there is multiple power domains
1034 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM

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