| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2600-pinctrl.yaml | 41 NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
65 NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
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| D | aspeed,ast2400-pinctrl.yaml | 44 NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
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| D | aspeed,ast2500-pinctrl.yaml | 57 NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2600-pinctrl.yaml | 43 NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
68 NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
|
| D | aspeed,ast2400-pinctrl.yaml | 43 NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
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| D | aspeed,ast2500-pinctrl.yaml | 53 NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | aspeed-g6-pinctrl.dtsi | 461 function = "NDTR1";
462 groups = "NDTR1";
|
| D | aspeed-g4.dtsi | 1013 function = "NDTR1";
1014 groups = "NDTR1";
|
| D | aspeed-g5.dtsi | 1171 function = "NDTR1";
1172 groups = "NDTR1";
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/aspeed/ |
| D | aspeed-g6-pinctrl.dtsi | 476 function = "NDTR1";
477 groups = "NDTR1";
|
| D | aspeed-g4.dtsi | 1016 function = "NDTR1";
1017 groups = "NDTR1";
|
| D | aspeed-g5.dtsi | 1180 function = "NDTR1";
1181 groups = "NDTR1";
|
| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | marvell_nand.c | 156 #define NDTR1 0x0C macro
326 * @ndtr1: Timing registers 1 value for this NAND chip
338 u32 ndtr1; member
446 /* NDTR1 fields */
777 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
2451 marvell_nand->ndtr1 = in marvell_nfc_setup_interface()
2462 marvell_nand->ndtr1 |= in marvell_nfc_setup_interface()
2719 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
|
| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | marvell_nand.c | 158 #define NDTR1 0x0C macro
332 * @ndtr1: Timing registers 1 value for this NAND chip
344 u32 ndtr1; member
454 /* NDTR1 fields */
785 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
2468 marvell_nand->ndtr1 = in marvell_nfc_setup_interface()
2479 marvell_nand->ndtr1 |= in marvell_nfc_setup_interface()
2730 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
|
| /kernel/linux/linux-6.6/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 746 SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC);
747 PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1);
748 FUNC_GROUP_DECL(NDTR1, U4);
2196 ASPEED_PINCTRL_GROUP(NDTR1),
2351 ASPEED_PINCTRL_FUNC(NDTR1),
|
| D | pinctrl-aspeed-g5.c | 724 SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
725 PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
726 FUNC_GROUP_DECL(NDTR1, P4);
2210 ASPEED_PINCTRL_GROUP(NDTR1),
2380 ASPEED_PINCTRL_FUNC(NDTR1),
|
| D | pinctrl-aspeed-g6.c | 718 SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4));
1991 ASPEED_PINCTRL_GROUP(NDTR1),
2231 ASPEED_PINCTRL_FUNC(NDTR1),
|
| /kernel/linux/linux-5.10/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 746 SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC);
747 PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1);
748 FUNC_GROUP_DECL(NDTR1, U4);
2196 ASPEED_PINCTRL_GROUP(NDTR1),
2351 ASPEED_PINCTRL_FUNC(NDTR1),
|
| D | pinctrl-aspeed-g5.c | 724 SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
725 PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
726 FUNC_GROUP_DECL(NDTR1, P4);
2210 ASPEED_PINCTRL_GROUP(NDTR1),
2380 ASPEED_PINCTRL_FUNC(NDTR1),
|
| D | pinctrl-aspeed-g6.c | 706 SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4));
1973 ASPEED_PINCTRL_GROUP(NDTR1),
2210 ASPEED_PINCTRL_FUNC(NDTR1),
|