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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun6i-a31.c221 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
236 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
247 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
249 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
251 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
253 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
255 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
257 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
259 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
261 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
[all …]
Dccu-sun8i-r40.c287 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
301 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
313 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
315 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
317 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
319 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
321 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
323 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
325 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
327 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-a33.c204 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
218 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
229 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
231 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
233 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
235 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
237 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
239 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
241 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
243 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
Dccu-sun8i-a23.c194 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
208 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
219 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
221 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
223 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
225 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
227 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
229 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
231 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
233 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
Dccu-sun50i-a64.c244 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
258 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
270 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
292 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
294 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
296 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
298 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
300 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
302 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
304 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-a83t.c257 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
264 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
275 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
295 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
297 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
299 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
301 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
303 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
305 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
307 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-h3.c168 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
182 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
193 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
215 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
217 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
219 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
221 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
223 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
225 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
227 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
Dccu-sun8i-v3s.c153 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
167 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
178 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
200 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
202 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
204 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
206 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
208 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
210 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
214 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu-sun6i-a31.c222 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
237 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
250 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
252 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
262 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
[all …]
Dccu-sun8i-r40.c288 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
302 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
314 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
318 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
320 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
322 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
324 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
326 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
328 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-a33.c205 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
219 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
232 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
234 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
Dccu-sun8i-a23.c195 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
209 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
220 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
222 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
234 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
Dccu-sun50i-a64.c246 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
260 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
272 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
294 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
296 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
298 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
300 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
302 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
304 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
306 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-a83t.c257 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
264 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
275 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
295 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
297 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
299 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
301 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
303 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
305 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
307 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
[all …]
Dccu-sun8i-h3.c170 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
184 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
195 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
217 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
219 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
221 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
223 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
225 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
227 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
229 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
[all …]
Dccu-sun8i-v3s.c166 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
180 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
191 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
213 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
215 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
217 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
219 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
221 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
223 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
227 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-ahb-clk.yaml22 - allwinner,sun6i-a31-ahb1-clk
62 const: allwinner,sun6i-a31-ahb1-clk
91 ahb1@1c20054 {
93 compatible = "allwinner,sun6i-a31-ahb1-clk";
96 clock-output-names = "ahb1";
104 clocks = <&ahb1>, <&pll6d2>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-ahb-clk.yaml22 - allwinner,sun6i-a31-ahb1-clk
62 const: allwinner,sun6i-a31-ahb1-clk
91 ahb1@1c20054 {
93 compatible = "allwinner,sun6i-a31-ahb1-clk";
96 clock-output-names = "ahb1";
104 clocks = <&ahb1>, <&pll6d2>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dallwinner,sun6i-a31-clock-reset.yaml20 - allwinner,sun6i-a31-ahb1-reset
40 - allwinner,sun6i-a31-ahb1-reset
57 compatible = "allwinner,sun6i-a31-ahb1-reset";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Darm-pl08x.yaml55 lli-bus-interface-ahb1:
63 mem-bus-interface-ahb1:
114 lli-bus-interface-ahb1;
134 /* Bus interface AHB1 (AHB0) is totally tilted */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dallwinner,sun6i-a31-clock-reset.yaml20 - allwinner,sun6i-a31-ahb1-reset
40 - allwinner,sun6i-a31-ahb1-reset
57 compatible = "allwinner,sun6i-a31-ahb1-reset";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Darm-pl08x.txt15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
45 lli-bus-interface-ahb1;
/kernel/linux/linux-6.6/drivers/clk/sunxi/
Dclk-simple-gates.c109 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
119 CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
125 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
131 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-simple-gates.c109 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
119 CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
125 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
131 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
Dclk-sun8i-bus-gates.c22 static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" }; in sun8i_h3_bus_gates_init()
23 enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent; in sun8i_h3_bus_gates_init() enumerator
68 clk_parent = AHB1; in sun8i_h3_bus_gates_init()

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