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/kernel/linux/linux-6.6/drivers/media/platform/samsung/exynos-gsc/
Dgsc-regs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
12 #include "gsc-core.h"
16 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
31 return -EBUSY; in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/exynos-gsc/
Dgsc-regs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
12 #include "gsc-core.h"
16 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
31 return -EBUSY; in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
[all …]
/kernel/linux/linux-6.6/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
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/kernel/linux/linux-6.6/drivers/media/platform/samsung/exynos4-is/
Dfimc-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
13 #include <media/drv-intf/exynos-fimc.h>
14 #include "media-dev.h"
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
[all …]
Dfimc-lite-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
12 #include <media/drv-intf/exynos-fimc.h>
14 #include "fimc-lite-reg.h"
15 #include "fimc-lite.h"
16 #include "fimc-core.h"
23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/
Dfimc-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
13 #include <media/drv-intf/exynos-fimc.h>
14 #include "media-dev.h"
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
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Dfimc-lite-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
12 #include <media/drv-intf/exynos-fimc.h>
14 #include "fimc-lite-reg.h"
15 #include "fimc-lite.h"
16 #include "fimc-core.h"
23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
18 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
20 * of the D-PHY specification (v2.1).
25 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_get_default_config() argument
30 if (!cfg) in phy_mipi_dphy_get_default_config()
31 return -EINVAL; in phy_mipi_dphy_get_default_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
41 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/s3c-camif/
Dcamif-regs.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "camif-regs.h"
13 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
14 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/samsung/s3c-camif/
Dcamif-regs.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "camif-regs.h"
13 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
14 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
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/kernel/linux/linux-6.6/tools/testing/selftests/bpf/prog_tests/
Dcore_extern.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
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/kernel/linux/linux-5.10/tools/testing/selftests/bpf/prog_tests/
Dcore_extern.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
53 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
55 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
57 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
59 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
60 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
62 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
[all …]
/kernel/linux/linux-6.6/drivers/pci/
Decam.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-ecam.h>
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
31 unsigned int bus_shift = ops->bus_shift; in pci_ecam_create()
32 struct pci_config_window *cfg; in pci_ecam_create() local
37 if (busr->start > busr->end) in pci_ecam_create()
[all …]
/kernel/linux/linux-5.10/drivers/pci/
Decam.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-ecam.h>
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
31 struct pci_config_window *cfg; in pci_ecam_create() local
36 if (busr->start > busr->end) in pci_ecam_create()
37 return ERR_PTR(-EINVAL); in pci_ecam_create()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/
Drpm.c1 // SPDX-License-Identifier: GPL-2.0
79 return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm2()
127 u64 cfg, last; in rpm_lmac_tx_enable() local
130 return -ENODEV; in rpm_lmac_tx_enable()
132 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
133 last = cfg; in rpm_lmac_tx_enable()
135 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
137 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
139 if (cfg != last) in rpm_lmac_tx_enable()
140 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
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/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeon_ep/
Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
48 #define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
53 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
54 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
55 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
56 #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind) argument
57 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
58 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
59 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
61 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
[all …]
/kernel/linux/linux-5.10/sound/pci/hda/
Dhda_auto_parser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BIOS auto-parser helper functions for HD-audio
38 return (int)(a->seq - b->seq); in compare_seq()
55 /* add the found input-pin to the cfg->inputs[] table */
56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
[all …]
/kernel/linux/linux-6.6/sound/pci/hda/
Dhda_auto_parser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BIOS auto-parser helper functions for HD-audio
38 return (int)(a->seq - b->seq); in compare_seq()
55 /* add the found input-pin to the cfg->inputs[] table */
56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-fimc.h"
117 return readl(ctx->regs + reg); in fimc_read()
122 writel(val, ctx->regs + reg); in fimc_write()
127 void __iomem *r = ctx->regs + reg; in fimc_set_bits()
134 void __iomem *r = ctx->regs + reg; in fimc_clear_bits()
141 u32 cfg; in fimc_sw_reset() local
144 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
145 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
166 u32 cfg; in fimc_set_type_ctrl() local
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-fimc.h"
115 return readl(ctx->regs + reg); in fimc_read()
120 writel(val, ctx->regs + reg); in fimc_write()
125 void __iomem *r = ctx->regs + reg; in fimc_set_bits()
132 void __iomem *r = ctx->regs + reg; in fimc_clear_bits()
139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
179 vco_optimal_index = -1; in pll_get_post_div()
201 if (vco_optimal_index == -1) { in pll_get_post_div()
207 pd->vco_freq = vco_optimal; in pll_get_post_div()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
179 vco_optimal_index = -1; in pll_get_post_div()
201 if (vco_optimal_index == -1) { in pll_get_post_div()
207 pd->vco_freq = vco_optimal; in pll_get_post_div()
[all …]
/kernel/linux/linux-6.6/arch/x86/pci/
Dmmconfig-shared.c1 // SPDX-License-Identifier: GPL-2.0
3 * mmconfig-shared.c - Low-level direct PCI config space access via
4 * MMCONFIG - common code between i386 and x86-64.
7 * - known chipset handling
8 * - ACPI decoding and validation
10 * Per-architecture code takes care of the mappings and accesses
37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
39 if (cfg->res.parent) in pci_mmconfig_remove()
40 release_resource(&cfg->res); in pci_mmconfig_remove()
41 list_del(&cfg->list); in pci_mmconfig_remove()
[all …]
/kernel/linux/linux-5.10/arch/x86/pci/
Dmmconfig-shared.c1 // SPDX-License-Identifier: GPL-2.0
3 * mmconfig-shared.c - Low-level direct PCI config space access via
4 * MMCONFIG - common code between i386 and x86-64.
7 * - known chipset handling
8 * - ACPI decoding and validation
10 * Per-architecture code takes care of the mappings and accesses
36 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
38 if (cfg->res.parent) in pci_mmconfig_remove()
39 release_resource(&cfg->res); in pci_mmconfig_remove()
40 list_del(&cfg->list); in pci_mmconfig_remove()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/microchip/wilc1000/
Dwlan_cfg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
140 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
148 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
151 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
152 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
158 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
161 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
162 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
168 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
[all …]

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