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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
29 compatible = "st,clkgen-c32";
34 compatible = "st,stih407-clkgen-plla9";
Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
Dst,clkgen-mux.txt13 "st,stih407-clkgen-a9-mux"
25 compatible = "st,stih407-clkgen-a9-mux";
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi161 clkgen: clock-controller@11800000 { label
162 compatible = "starfive,jh7100-clkgen";
178 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
179 <&clkgen JH7100_CLK_I2C0_APB>;
191 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
192 <&clkgen JH7100_CLK_I2C1_APB>;
206 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
218 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
219 <&clkgen JH7100_CLK_UART2_APB>;
231 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll1"
14 "st,stih407-clkgen-plla9"
15 "st,stih418-clkgen-plla9"
26 compatible = "st,clkgen-c32";
31 compatible = "st,stih407-clkgen-plla9";
Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
43 compatible = "st,stih407-clkgen-a9-mux";
65 compatible = "st,clkgen-c32";
70 compatible = "st,clkgen-pll0-a0";
86 compatible = "st,clkgen-c32";
91 compatible = "st,clkgen-pll0-c0";
98 compatible = "st,clkgen-pll1-c0";
140 compatible = "st,clkgen-c32";
163 compatible = "st,clkgen-c32";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtango4-common.dtsi21 clocks = <&clkgen CPU_CLK>;
74 clkgen: clkgen@10000 { label
75 compatible = "sigma,tango4-clkgen";
105 clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
113 clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
129 clocks = <&clkgen USB_CLK>;
144 clocks = <&clkgen USB_CLK>;
151 clocks = <&clkgen SYS_CLK>;
Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
73 compatible = "st,clkgen-c32";
78 compatible = "st,clkgen-pll0";
112 compatible = "st,clkgen-c32";
117 compatible = "st,clkgen-pll0";
126 compatible = "st,clkgen-pll1";
219 compatible = "st,clkgen-c32";
255 compatible = "st,clkgen-c32";
[all …]
Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
72 compatible = "st,clkgen-c32";
77 compatible = "st,clkgen-pll0";
114 compatible = "st,clkgen-c32";
119 compatible = "st,clkgen-pll0";
129 compatible = "st,clkgen-pll1";
225 compatible = "st,clkgen-c32";
261 compatible = "st,clkgen-c32";
[all …]
Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux";
72 compatible = "st,clkgen-c32";
77 compatible = "st,clkgen-pll0";
113 compatible = "st,clkgen-c32";
118 compatible = "st,clkgen-pll0";
128 compatible = "st,clkgen-pll1";
217 compatible = "st,clkgen-c32";
251 compatible = "st,clkgen-c32";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Daxi-clkgen.txt1 Binding for the axi-clkgen clock generator
8 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
10 - reg : Address and length of the axi-clkgen register set.
21 compatible = "adi,axi-clkgen";
Dtango4-clock.txt9 - compatible: should be "sigma,tango4-clkgen".
17 clkgen: clkgen@10000 {
18 compatible = "sigma,tango4-clkgen";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
50 compatible = "adi,axi-clkgen-2.00.a";
Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
Dstarfive,jh7100-audclk.yaml52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
53 <&clkgen JH7100_CLK_AUDIO_12288>,
54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
Dstarfive,jh7100-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
15 const: starfive,jh7100-clkgen
51 compatible = "starfive,jh7100-clkgen";
/kernel/linux/linux-6.6/drivers/clk/st/
DMakefile2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
Dclkgen-mux.c3 * clkgen-mux.c: ST GEN-MUX Clock driver
16 #include "clkgen.h"
110 CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
/kernel/linux/linux-5.10/drivers/clk/st/
DMakefile2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
Dclkgen-mux.c3 * clkgen-mux.c: ST GEN-MUX Clock driver
16 #include "clkgen.h"
100 CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c52 *| | clk-125/txclk | clkgen |
53 *| | clkgen | |
56 *| | |clkgen/phyclk-in |
69 * clkgen| 1 | 1 | n/a |
85 * clkgen| | |
91 * clkgen| | |
177 /* On GiGa clk source can be either ext or from clkgen */ in stih4xx_fix_retime_src()
181 /* Switch to clkgen for these speeds */ in stih4xx_fix_retime_src()

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