Searched +full:hi3559av100 +full:- +full:clock (Results 1 – 3 of 3) sorted by relevance
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | hisilicon,hi3559av100-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon SOC Clock for HI3559AV100
10 - Dongjiu Geng <gengdongjiu@huawei.com>
13 Hisilicon SOC clock control module which supports the clocks, resets and
14 power domains on HI3559AV100.
17 dt-bindings/clock/hi3559av100-clock.h
22 - hisilicon,hi3559av100-clock
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| /kernel/linux/linux-6.6/drivers/clk/hisilicon/ |
| D | clk-hi3559a.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon Hi3559A clock driver
5 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/hi3559av100-clock.h>
385 val = readl_relaxed(clk->ctrl_reg1); in clk_pll_set_rate()
386 val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); in clk_pll_set_rate()
387 val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); in clk_pll_set_rate()
388 val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift); in clk_pll_set_rate()
390 val |= frac_val << clk->frac_shift; in clk_pll_set_rate()
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| /kernel/linux/patches/linux-5.10/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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