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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive Watchdog for JH7100 and JH7110 SoC
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
19 isn't cleared, the watchdog will reset the system unless the watchdog
20 reset is disabled.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dstarfive,jh7100-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 SoC Reset Controller
10 - Emil Renner Berthing <kernel@esmil.dk>
15 - starfive,jh7100-reset
20 "#reset-cells":
24 - compatible
25 - reg
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/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
12 compatible = "starfive,jh7100";
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/hwmon/
Dstarfive,jh71x0-temp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Emil Renner Berthing <kernel@esmil.dk>
18 - starfive,jh7100-temp
19 - starfive,jh7110-temp
28 clock-names:
30 - const: sense
31 - const: bus
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/kernel/linux/linux-6.6/drivers/reset/starfive/
Dreset-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7100 SoC
11 #include "reset-starfive-jh71x0.h"
13 #include <dt-bindings/reset/starfive-jh7100.h>
28 * Most reset lines have their status inverted so a 0 bit in the STATUS
54 return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node, in jh7100_reset_probe()
63 { .compatible = "starfive,jh7100-reset" },
69 .name = "jh7100-reset",
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "StarFive JH7100 Reset Driver"
12 This enables the reset controller driver for the StarFive JH7100 SoC.
15 bool "StarFive JH7110 Reset Driver"
21 This enables the reset controller driver for the StarFive JH7110 SoC.
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
4 obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
5 obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Pin Controller
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
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/kernel/linux/linux-6.6/Documentation/process/
Dmaintainer-soc.rst1 .. SPDX-License-Identifier: GPL-2.0
8 --------
10 The SoC subsystem is a place of aggregation for SoC-specific code.
13 * devicetrees for 32- & 64-bit ARM and RISC-V
14 * 32-bit ARM board files (arch/arm/mach*)
15 * 32- & 64-bit ARM defconfigs
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
17 ARM, RISC-V and Loongarch
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
20 other top-level maintainers. The drivers/soc/ directory is generally meant
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/kernel/linux/linux-6.6/drivers/watchdog/
Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/reset.h>
17 /* JH7100 Watchdog register define */
35 * [0]: reset enable;
83 unsigned int control; /* Watchdog Control Resgister for reset enable */
112 /* Register layout and configuration for the JH7100 */
150 ret = clk_prepare_enable(wdt->apb_clk); in starfive_wdt_enable_clock()
152 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n"); in starfive_wdt_enable_clock()
154 ret = clk_prepare_enable(wdt->core_clk); in starfive_wdt_enable_clock()
156 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n"); in starfive_wdt_enable_clock()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
51 bool "Update boot-enabled watchdog until userspace takes over"
77 bool "Enable watchdog hrtimer-based pretimeouts"
178 to toggle reset line if SoC fails to ping watchdog via GPIO.
190 cause system reset.
228 tristate "Watchdog device controlled through GPIO-line"
233 controlled through GPIO-line.
287 the watchdog triggers the system will be reset.
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/kernel/linux/linux-6.6/drivers/hwmon/
Dsfctemp.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/reset.h>
19 * TempSensor reset. The RSTN can be de-asserted once the analog core has
21 * 0:reset 1:de-assert
27 * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the
41 * Temp(C)=DOUT*Y/4094 - K
65 writel(SFCTEMP_PD, sfctemp->regs); in sfctemp_power_up()
68 writel(0, sfctemp->regs); in sfctemp_power_up()
72 /* de-assert reset */ in sfctemp_power_up()
73 writel(SFCTEMP_RSTN, sfctemp->regs); in sfctemp_power_up()
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/kernel/linux/linux-6.6/drivers/pinctrl/starfive/
Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7100 SoC
17 #include <linux/reset.h>
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
36 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
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/kernel/linux/linux-6.6/drivers/tty/serial/8250/
D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/reset.h>
72 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
76 value |= d->msr_mask_on; in dw8250_modify_msr()
77 value &= ~d->msr_mask_off; in dw8250_modify_msr()
95 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
96 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
101 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
106 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
110 while (tries--) { in dw8250_check_lcr()
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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