| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | ti,j721e-system-controller.yaml | 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
100 /* SERDES4 lane0/1/2/3 select */
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | analogix,anx7625.yaml | 45 analogix,lane0-swing:
50 an array of swing register setting for DP tx lane0 PHY.
78 DP TX lane1 swing register setting same with lane0
79 swing, please refer lane0-swing property description.
149 analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
|
| /kernel/linux/linux-6.6/drivers/phy/amlogic/ |
| D | phy-meson-g12a-usb3-pcie.c | 215 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus in phy_g12a_usb3_init()
228 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in phy_g12a_usb3_init()
229 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in phy_g12a_usb3_init()
230 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 in phy_g12a_usb3_init()
231 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in phy_g12a_usb3_init()
248 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 in phy_g12a_usb3_init()
249 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 in phy_g12a_usb3_init()
250 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in phy_g12a_usb3_init()
|
| /kernel/linux/linux-5.10/drivers/phy/amlogic/ |
| D | phy-meson-g12a-usb3-pcie.c | 215 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus in phy_g12a_usb3_init()
228 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in phy_g12a_usb3_init()
229 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in phy_g12a_usb3_init()
230 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 in phy_g12a_usb3_init()
231 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in phy_g12a_usb3_init()
248 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 in phy_g12a_usb3_init()
249 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 in phy_g12a_usb3_init()
250 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in phy_g12a_usb3_init()
|
| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-ipq806x-usb.c | 341 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode in qcom_ipq806x_usb_ss_phy_init()
364 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in qcom_ipq806x_usb_ss_phy_init()
365 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
366 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
367 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
385 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
386 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 in qcom_ipq806x_usb_ss_phy_init()
387 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in qcom_ipq806x_usb_ss_phy_init()
|
| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-ipq806x-usb.c | 345 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode in qcom_ipq806x_usb_ss_phy_init()
368 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 in qcom_ipq806x_usb_ss_phy_init()
369 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
370 * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
371 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 in qcom_ipq806x_usb_ss_phy_init()
389 * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version in qcom_ipq806x_usb_ss_phy_init()
390 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110 in qcom_ipq806x_usb_ss_phy_init()
391 * LANE0.TX_OVRD_DRV_LO.EN set to 1. in qcom_ipq806x_usb_ss_phy_init()
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,msm8996-qmp-pcie-phy.yaml | 87 - lane0
|
| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 187 * lane0: USB3/GbE1 PHY Configuration 1
208 * lane0: USB3/GbE1 PHY Status 1
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
|
| /kernel/linux/linux-6.6/drivers/phy/starfive/ |
| D | phy-jh7110-dphy-rx.c | 61 * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
86 /* SERDES4 lane0/1/2/3 select */
|
| D | k3-j7200-main.dtsi | 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3568.dtsi | 157 /* bifurcation; lane0 when using 1+1 */
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 242 uint8_t lane0:2; /* Mapping for lane 0 */ member
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
|
| D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 242 uint8_t lane0:2; /* Mapping for lane 0 */ member
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
|
| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 210 /* HS RX Control of lane0 */ in rk_dphy_enable()
|
| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 211 /* HS RX Control of lane0 */ in rk_dphy_enable()
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-main.dtsi | 51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
56 /* SERDES4 lane0/1/2/3 select */
|