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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Datmel,lcdc.txt1 Atmel LCDC Framebuffer
2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 "atmel,at32ap-lcdc"
[all …]
Dmarvell,pxa2xx-lcdc.txt2 ------------------
5 - compatible : one of these
6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
9 - reg : should contain 1 register range (address and length).
10 - interrupts : framebuffer controller interrupt.
11 - clocks: phandle to input clocks
14 - lcd-supply: A phandle to a power regulator that controls the LCD voltage.
17 - port: connection to the LCD panel (see video-interfaces.txt)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Datmel,lcdc.txt1 Atmel LCDC Framebuffer
2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 - reg : Should contain 1 register ranges(address and length).
[all …]
Dmarvell,pxa2xx-lcdc.txt2 ------------------
5 - compatible : one of these
6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
9 - reg : should contain 1 register range (address and length).
10 - interrupts : framebuffer controller interrupt.
11 - clocks: phandle to input clocks
14 - lcd-supply: A phandle to a power regulator that controls the LCD voltage.
17 - port: connection to the LCD panel (see video-interfaces.txt)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/
Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
28 avdd1v0-supply:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/
Drockchip-lvds.txt5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
17 - avdd3v3-supply: regulator phandle for 3.3V analog power
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/
Drockchip-io-domain.txt2 -------------------------------------
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
38 - "rockchip,rk3288-io-voltage-domain" for rk3288
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-fb.txt6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
20 - lcd-supply: Regulator for LCD supply voltage.
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
[all …]
/kernel/linux/linux-5.10/arch/sh/include/asm/
Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
96 /* Display types supported by the LCDC */
120 /* LCDC Pixclock sources */
128 /* LCDC pixclock input divider. Set to 1 at a minimum! */
148 * Display Enable signal (default high-active) DISPEN_LOWACT
149 * Display Data signals (default high-active) DPOL_LOWACT
[all …]
/kernel/linux/linux-6.6/arch/sh/include/asm/
Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
96 /* Display types supported by the LCDC */
120 /* LCDC Pixclock sources */
128 /* LCDC pixclock input divider. Set to 1 at a minimum! */
148 * Display Enable signal (default high-active) DISPEN_LOWACT
149 * Display Data signals (default high-active) DPOL_LOWACT
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
51 - rockchip,rk3228-io-voltage-domain
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpxa300-raumfeld-controller.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300";
11 reg_vbatt: regulator-vbatt {
12 compatible = "regulator-fixed";
13 regulator-name = "vbatt-fixed-supply";
14 regulator-min-microvolt = <3700000>;
15 regulator-max-microvolt = <3700000>;
16 regulator-always-on;
[all …]
Dimx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
10 …compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25…
13 model = "CMO-QVGA";
14 bits-per-pixel = <16>;
16 bus-width = <18>;
17 display-timings {
18 native-mode = <&qvga_timings>;
20 clock-frequency = <6500000>;
[all …]
Drk3288-rock2-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/pwm/pwm.h>
12 emmc_pwrseq: emmc-pwrseq {
13 compatible = "mmc-pwrseq-emmc";
14 pinctrl-0 = <&emmc_reset>;
15 pinctrl-names = "default";
16 reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
19 ext_gmac: external-gmac-clock {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/pxa/
Dpxa300-raumfeld-controller.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300";
11 reg_vbatt: regulator-vbatt {
12 compatible = "regulator-fixed";
13 regulator-name = "vbatt-fixed-supply";
14 regulator-min-microvolt = <3700000>;
15 regulator-max-microvolt = <3700000>;
16 regulator-always-on;
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dsh7760fb.c1 // SPDX-License-Identifier: GPL-2.0
3 * SH7760/SH7763 LCDC Framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
11 * Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
19 #include <linux/dma-mapping.h>
56 /* wait_for_lps - wait until power supply has reached a certain state. */
60 while (--i && ((ioread16(par->base + LDPMMR) & 3) != val)) in wait_for_lps()
64 return -ETIMEDOUT; in wait_for_lps()
69 /* en/disable the LCDC */
72 struct sh7760fb_par *par = info->par; in sh7760fb_blank()
[all …]
Dsh_mobile_lcdcfb.c2 * SuperH Mobile LCDC Framebuffer
16 #include <linux/dma-mapping.h>
36 /* ----------------------------------------------------------------------------
148 * struct sh_mobile_lcdc_overlay - LCDC display overlay
150 * @channel: LCDC channel this overlay belongs to
153 * @index: Overlay index (0-3)
157 * @alpha: Global alpha blending value (0-255, for alpha blending mode)
218 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
221 /* -----------------------------------------------------------------------------
285 return chan->cfg->chan == LCDC_CHAN_SUBLCD; in lcdc_chan_is_sublcd()
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/
Dsh7760fb.c1 // SPDX-License-Identifier: GPL-2.0
3 * SH7760/SH7763 LCDC Framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
11 * Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
19 #include <linux/dma-mapping.h>
56 /* wait_for_lps - wait until power supply has reached a certain state. */
60 while (--i && ((ioread16(par->base + LDPMMR) & 3) != val)) in wait_for_lps()
64 return -ETIMEDOUT; in wait_for_lps()
69 /* en/disable the LCDC */
72 struct sh7760fb_par *par = info->par; in sh7760fb_blank()
[all …]
Dsh_mobile_lcdcfb.c2 * SuperH Mobile LCDC Framebuffer
16 #include <linux/dma-mapping.h>
35 /* ----------------------------------------------------------------------------
147 * struct sh_mobile_lcdc_overlay - LCDC display overlay
149 * @channel: LCDC channel this overlay belongs to
152 * @index: Overlay index (0-3)
156 * @alpha: Global alpha blending value (0-255, for alpha blending mode)
217 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
220 /* -----------------------------------------------------------------------------
284 return chan->cfg->chan == LCDC_CHAN_SUBLCD; in lcdc_chan_is_sublcd()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Dam335x-myirtech-myd.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
4 /* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
6 /dts-v1/;
8 #include "am335x-myirtech-myc.dtsi"
10 #include <dt-bindings/display/tda998x.h>
11 #include <dt-bindings/input/input.h>
14 model = "MYIR MYD-AM335X";
15 compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx";
18 stdout-path = &uart0;
[all …]
/kernel/linux/linux-5.10/drivers/soc/rockchip/
Dio-domain.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
79 static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply, in rockchip_iodomain_write() argument
82 struct rockchip_iodomain *iod = supply->iod; in rockchip_iodomain_write()
88 val <<= supply->idx; in rockchip_iodomain_write()
90 /* apply hiword-mask */ in rockchip_iodomain_write()
91 val |= (BIT(supply->idx) << 16); in rockchip_iodomain_write()
93 ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val); in rockchip_iodomain_write()
95 dev_err(iod->dev, "Couldn't write to GRF\n"); in rockchip_iodomain_write()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6sx-udoo-neo.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 stdout-path = "serial0:115200n8";
16 compatible = "gpio-leds";
18 led-red {
19 label = "udoo-neo:red:mmc";
21 default-state = "off";
22 linux,default-trigger = "mmc0";
25 led-orange {
26 label = "udoo-neo:orange:user";
28 default-state = "keep";
[all …]
Dimx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
10 …compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25…
13 model = "CMO-QVGA";
14 bits-per-pixel = <16>;
16 bus-width = <18>;
17 display-timings {
18 native-mode = <&qvga_timings>;
20 clock-frequency = <6500000>;
[all …]
/kernel/linux/linux-6.6/drivers/soc/rockchip/
Dio-domain.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
71 int (*write)(struct rockchip_iodomain_supply *supply, int uV);
79 int (*write)(struct rockchip_iodomain_supply *supply, int uV);
82 static int rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uV) in rk3568_iodomain_write() argument
84 struct rockchip_iodomain *iod = supply->iod; in rk3568_iodomain_write()
89 switch (supply->idx) { in rk3568_iodomain_write()
93 b = supply->idx; in rk3568_iodomain_write()
95 b = supply->idx + 4; in rk3568_iodomain_write()
[all …]

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