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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/ufs/
Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
25 clock-names:
27 - const: fck
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/renesas/
Dr8a779f0-spider-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
11 #include "r8a779f0.dtsi"
15 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
24 stdout-path = "serial0:1843200n8";
28 compatible = "gpio-leds";
30 led-7 {
34 function-enumerator = <7>;
37 led-8 {
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Dr8a779f0.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
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/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr8a779f0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
7 * Based on r8a779a0-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
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/kernel/linux/linux-6.6/drivers/ufs/host/
Dufs-renesas.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Renesas UFS host controller driver
17 #include <ufs/ufshcd.h>
19 #include "ufshcd-pltfrm.h"
287 WARN_ON(p->index >= MAX_INDEX); in ufs_renesas_reg_control()
289 switch (p->mode) { in ufs_renesas_reg_control()
291 ufshcd_writel(hba, save[p->index], p->reg); in ufs_renesas_reg_control()
294 save[p->index] |= p->u.set; in ufs_renesas_reg_control()
297 save[p->index] = ufshcd_readl(hba, p->reg) & p->mask; in ufs_renesas_reg_control()
300 ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg, in ufs_renesas_reg_control()
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