| /arkcompiler/ets_frontend/es2panda/compiler/core/ |
| D | regAllocator.cpp | 79 auto regCnt = ins->Registers(®s); in Run()
84 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run() local
87 if (!CheckRegIndices(ins, registers)) { in Run()
98 auto regCnt = ins->Registers(®s); in Run()
100 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run() local
103 if (!CheckRegIndices(ins, registers)) { in Run()
127 auto regCnt = ins->Registers(®s); in AdjustInsRegWhenHasSpill()
133 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in AdjustInsRegWhenHasSpill() local
134 for (auto *reg : registers) { in AdjustInsRegWhenHasSpill()
138 if (CheckRegIndices(ins, registers, ®sKind)) { in AdjustInsRegWhenHasSpill()
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| /arkcompiler/runtime_core/static_core/irtoc/backend/compiler/ |
| D | codegen_fastpath.h | 27 …* save/restore registers before calling native functions. These intrinsics pushes caller saved reg…
30 * Compiled code(caller) saves only parameter registers.
31 …* Fast path entrypoint saves only used registers, and saves all caller registers if it goes to the…
32 … path is invoked via code-to-runtime bridge, which forms boundary frame and saves callee registers.
33 * So, before calling the slow path we restore all modified callee registers.
35 …mented entrypoint (slow path) we need a separate bridge, because it shouldn't save caller registers
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| /arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/ |
| D | reg_map.h | 27 …* Since the set of available codegen's registers can be sparse, we create local regalloc registers…
28 …* equal to the number of given registers and save map to restore actual codegen register number fr…
32 * - there are 3 available registers: r16, r18, r20;
36 …* - RegAlloc locally assigns registers with numbers 0, 1 and 2 and then replace them by the codege…
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| D | reg_map.cpp | 24 // Firstly map registers available for register allocator starting with the highest priority one in SetMask()
32 // Add caller registers in SetMask()
40 // Now map unavailable registers, since they can be assigned to the instructions in SetMask()
52 // Add caller registers in SetCallerFirstMask()
59 // Add caller registers after callees onece in SetCallerFirstMask()
67 // Add callee registers in SetCallerFirstMask()
75 // Now map unavailable registers, since they can be assigned to the instructions in SetCallerFirstMask()
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/optimizations/regalloc/ |
| D | reg_map.h | 27 …* Since the set of available codegen's registers can be sparse, we create local regalloc registers…
28 …* equal to the number of given registers and save map to restore actual codegen register number fr…
32 * - there are 3 available registers: r16, r18, r20;
36 …* - RegAlloc locally assigns registers with numbers 0, 1 and 2 and then replace them by the codege…
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| D | reg_map.cpp | 25 // Firstly map registers available for register allocator starting with the highest priority one in SetMask()
34 // Add caller registers in SetMask()
42 // Now map unavailable registers, since they can be assigned to the instructions in SetMask()
54 // Add caller registers in SetCallerFirstMask()
61 // Add caller registers after callees onece in SetCallerFirstMask()
70 // Add callee registers in SetCallerFirstMask()
78 // Now map unavailable registers, since they can be assigned to the instructions in SetCallerFirstMask()
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/ |
| D | x64_abi.cpp | 26 /* integer registers */ in IsAvailableReg()
35 /* fp-simd registers */ in IsAvailableReg()
49 /* integer registers */ in IsCalleeSavedReg()
58 /* fp-simd registers */ in IsCalleeSavedReg()
72 /* integer registers */ in IsSpillReg()
81 /* fp-simd registers */ in IsSpillReg()
95 /* integer registers */ in IsExtraSpillReg()
104 /* fp-simd registers */ in IsExtraSpillReg()
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| /arkcompiler/runtime_core/bytecode_optimizer/ |
| D | reg_encoder.h | 29 * |<-locals->|<-free registers->|<-RegAlloc temps->|<-arguments->|
33 * * locals (>= 0) are registers allocated for function's local variables;
34 * * temps (>= 0) are temporary registers that can be allocated by spill-fill
36 * * arguments (>= 0) are registers allocated for function's arguemnts.
41 * (or temps) then all registers go strictly in order without "holes".
46 * number of registers used in the unoptimized bytecode. Total number of arguments
52 * range temps from free registers if necessary, consistently changing all register
55 * |<-locals->|<-range temps->|<-RegAlloc temps->|<-arguments->|<-free registers->|
58 * actual inputs r16+. If such instructions are found, some lower registers
59 * (starting with r0, but no more than MAX_NUM_INPUTS registers) are reserved as
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| /arkcompiler/ets_frontend/ets2panda/compiler/core/ |
| D | regAllocator.cpp | 87 …::size_t> RegAllocatorBase::RegIndicesValid(const IRNode *const ins, const Span<VReg *> ®isters) in RegIndicesValid() argument
100 if (std::all_of(registers.begin(), registers.end(), in RegIndicesValid()
149 const auto regCnt = ins->Registers(®s); in Run()
150 const auto registers = in Run() local
156 const auto [indices_valid, limit] = RegIndicesValid(ins, registers); in Run()
165 for (auto *const reg : registers) { in Run()
175 for (auto *const reg : registers) { in Run()
218 const auto regCnt = ins->Registers(®s); in Run()
219 const auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run() local
220 if (RegIndicesValid(ins, registers).first) { in Run()
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| /arkcompiler/runtime_core/static_core/bytecode_optimizer/ |
| D | reg_encoder.h | 29 * |<-locals->|<-free registers->|<-RegAlloc temps->|<-arguments->|
33 * * locals (>= 0) are registers allocated for function's local variables;
34 * * temps (>= 0) are temporary registers that can be allocated by spill-fill
36 * * arguments (>= 0) are registers allocated for function's arguemnts.
41 * (or temps) then all registers go strictly in order without "holes".
46 * number of registers used in the unoptimized bytecode. Total number of arguments
52 * range temps from free registers if necessary, consistently changing all register
55 * |<-locals->|<-range temps->|<-RegAlloc temps->|<-arguments->|<-free registers->|
58 * actual inputs r16+. If such instructions are found, some lower registers
59 * (starting with r0, but no more than MAX_NUM_INPUTS registers) are reserved as
[all …]
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/ |
| D | aarch64_abi.cpp | 31 /* integer registers */ in IsAvailableReg()
40 /* fp-simd registers */ in IsAvailableReg()
63 /* integer registers */ in IsCalleeSavedReg()
72 /* fp-simd registers */ in IsCalleeSavedReg()
89 /* integer registers */ in IsSpillReg()
98 /* fp-simd registers */ in IsSpillReg()
115 /* integer registers */ in IsExtraSpillReg()
124 /* fp-simd registers */ in IsExtraSpillReg()
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/ |
| D | x64_isa.h | 46 /* Registers in x64 state */
49 /* integer registers */
57 /* fp-simd registers */
64 /* integer registers alias */
120 * We save callee-saved registers from lower stack area to upper stack area.
121 * If possible, we store a pair of registers (int/int and fp/fp) in the stack.
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| D | x64_int_regs.def | 17 * Registers in x86-64
19 * - caller-save registers: %rax, %rcx, %rdx, %rdi, %rsi, %rsp, and %r8-r11
20 * - callee-saved registers: %r12, %r13, %r14, %r15, %rbx, %rsp, %rbp.
22 * the caller. So, It's caller-save registers
23 …* - User-level applications use as integer registers for passing the sequence %rdi, %rsi, %rdx, %r…
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/ |
| D | encoder.md | 12 …registers, which are used in the target architecture: amount of available registers, theirs type a…
22 CallingConvention - is class for control calls/jumps, for spill/fill registers and access for nativ…
31 | don't fit in registers
41 Header | scalar registers | |
43 | vector registers | |
52 Header | scalar registers | |
54 | vector registers | |
141 // memory with base , index registers and scale
175 // Get special registers data
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| D | encode.h | 330 virtual void SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
331 virtual void LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
333 * Save/load registers to/from the memory.
335 …* If `mask` is empty (all bits are zero), then registers will be saved densely, otherwise place fo…
337 * Example: registers' bits = [1, 3, 10], mask's bits = [0, 1, 2, 3, 8, 9, 10, 11]
338 …* We can see that mask has the gap in 4-7 bits. So, registers will be saved in the following slots:
345 * @param registers mask of registers to be saved
346 * @param is_fp if true, registers are floating point registers
349 * @param mask determine memory layout for the registers
351 virtual void SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask);
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/ |
| D | memlayout.h | 30 * Function arguments that are not passed through registers
36 * we store call-saved registers if any.
39 * Args passed via registers according to the architecture-specific ABI
43 * loaded into registers when needed, and stored back to the memory when
63 * a register-spill area and space for caller-saved registers
67 * that cannot be passed through registers, it is the caller's
171 * passed through registers
179 * through registers because a call passes more than 8 arguments, or
180 * they cannot be fit in a pair of registers.
187 * "Pseudo-registers can be regarded as local variables of a
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| /arkcompiler/runtime_core/static_core/compiler/docs/ |
| D | plt.md | 10 …lob is generated for each place it is called, and as it contains saving registers and setting up o…
30 parameters are already in proper registers):
55 `PLT CallStatic Resolver` after saving all registers to the stack and `BoundaryFrame` generation, h…
95 . . . ; Save caller-saved registers
103 Unlike CallStatic, there is no way to use default parameter registers to send/receive values into r…
188 * **Save caller-saved registers.**
189 In CallStatic resolver we prepare place on the stack and save registers there. In three other Resol…
190 registers are saved directly into appropriate places in previous CFrame.
192 Moreover, for `arm64` we manually add `x16` to live registers set.
197 * **Save callee-saved registers.**
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| /arkcompiler/runtime_core/compiler/docs/ |
| D | plt.md | 10 …lob is generated for each place it is called, and as it contains saving registers and setting up o…
30 parameters are already in proper registers):
55 `PLT CallStatic Resolver` after saving all registers to the stack and `BoundaryFrame` generation, h…
95 . . . ; Save caller-saved registers
103 Unlike CallStatic, there is no way to use default parameter registers to send/receive values into r…
188 * **Save caller-saved registers.**
189 In CallStatic resolver we prepare place on the stack and save registers there. In three other Resol…
190 registers are saved directly into appropriate places in previous CFrame.
192 Moreover, for `arm64` we manually add `x16` to live registers set.
197 * **Save callee-saved registers.**
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| /arkcompiler/runtime_core/docs/ |
| D | rationale-for-bytecode.md | 23 that the number and purpose of registers differs, too. Some nuances of working with stack may also
36 hardware world: the terms "operations", "operands", "registers" and "stack" have the same meaning.
37 In case there is a chance for ambiguity, the terms "virtual registers" and "virtual stack" are used
133 Let's take a closer look at `adda arg1, arg2`. Assume that arguments map to virtual registers on
148 It easy to see that to address virtual registers 4 and 5 we need just 3 bits which allows to encode
157 to the stack-based approach. Of course, if virtual registers have large numbers that do no fit
168 function arguments to virtual registers with larger numbers reserving smaller ones for local
216 There may be another concern: Does a statically-typed bytecode imply statically-typed registers?
217 I.e. does it mean that if `adda reg1, reg2` operates only on 64-bit integers, registers `reg1`
219 no, they must not, virtual registers may hold value of different types (just as hardware registers,
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| D | code_metainfo.md | 5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
9 registers which are live during this call instruction. Since all virtual regisetrs should be saved …
106 | CALLEE_REG_MASK | Specifies registers mask that is saved in the method |
107 | CALLEE_FP_REG_MASK | Specifies fp registers mask that is saved in the method |
109 | VREGS_COUNT | Number of virtual registers in reg map |
120 | ROOTS_REG_MASK_INDEX | Mask of the CPU registers that hold managed objects |
123 | VREG_MASK_INDEX | Mask of the virtual registers, that are modified from the last stackmap to the …
124 | VREG_MAP_INDEX | Map of the virtual registers, that are modified from the last stackmap to the cu…
137 | VREGS_COUNT | Number of virtual registers, that belongs to this inlined method |
139 Stackmap and all its inlined infos use same Virtual registers map, but separate it via `VREGS_COUNT…
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| /arkcompiler/runtime_core/static_core/docs/ |
| D | rationale-for-bytecode.md | 23 that the number and purpose of registers differs, too. Some nuances of working with stack may also
36 hardware world: the terms "operations", "operands", "registers" and "stack" have the same meaning.
37 In case there is a chance for ambiguity, the terms "virtual registers" and "virtual stack" are used
133 Let's take a closer look at `adda arg1, arg2`. Assume that arguments map to virtual registers on
148 It easy to see that to address virtual registers 4 and 5 we need just 3 bits which allows to encode
157 to the stack-based approach. Of course, if virtual registers have large numbers that do no fit
168 function arguments to virtual registers with larger numbers reserving smaller ones for local
216 There may be another concern: Does a statically-typed bytecode imply statically-typed registers?
217 I.e. does it mean that if `adda reg1, reg2` operates only on 64-bit integers, registers `reg1`
219 no, they must not, virtual registers may hold value of different types (just as hardware registers,
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| D | code_metainfo.md | 5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
9 registers which are live during this call instruction. Since all virtual regisetrs should be saved …
106 | CALLEE_REG_MASK | Specifies registers mask that is saved in the method |
107 | CALLEE_FP_REG_MASK | Specifies fp registers mask that is saved in the method |
109 | VREGS_COUNT | Number of virtual registers in reg map |
120 | ROOTS_REG_MASK_INDEX | Mask of the CPU registers that hold managed objects |
123 | VREG_MASK_INDEX | Mask of the virtual registers, that are modified from the last stackmap to the …
124 | VREG_MAP_INDEX | Map of the virtual registers, that are modified from the last stackmap to the cu…
137 | VREGS_COUNT | Number of virtual registers, that belongs to this inlined method |
139 Stackmap and all its inlined infos use same Virtual registers map, but separate it via `VREGS_COUNT…
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| D | on-stack-replacement.md | 70 This instruction contains information about all live virtual registers at the enter to the loop.
77 To do this, we need to know all live virtual registers at this moment.
85 1. move all constants to the cpu registers or frame slots by inserting move or store instructions
88 … first point is necessary because the Panda compiler can place some constants in the cpu registers,
89 but the constants themselves are not virtual registers and won't be stored in the metainfo.
90 Accordingly, they need to be restored back to the CPU registers or frame slots.
92 Osr stackmaps (OsrStateStamp) are needed to restore virtual registers.
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| /arkcompiler/runtime_core/assembler/templates/ |
| D | ins_emit.h.erb | 160 auto registers = regs;
167 % registers = i.operands.select(&:reg?)
168 if (registers.size() < <%= registers.size + 1 %>) {
169 while (registers.size() < <%= registers.size %>) {
170 registers.push_back(0);
172 emitter.<%= i.emitter_name %>(<%= operands(i, "registers").join(", ") %>);
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| /arkcompiler/runtime_core/static_core/assembler/templates/ |
| D | ins_emit.h.erb | 155 auto registers = regs;
162 % registers = i.operands.select(&:reg?)
163 if (registers.size() < <%= registers.size + 1 %>) {
164 while (registers.size() < <%= registers.size %>) {
165 registers.push_back(0);
167 emitter.<%= i.emitter_name %>(<%= operands(i, "registers").join(", ") %>);
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