Searched +full:supervisor +full:- +full:mode (Results 1 – 25 of 240) sorted by relevance
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| /kernel/linux/linux-5.10/arch/m68k/ifpsp060/ |
| D | os.S | 3 |M68000 Hi-Performance Microprocessor Division
5 |Production Release P1.00 -- October 10, 1994
32 | - example "Call-Out"s required by both the ISP and FPSP.
38 | EXAMPLE CALL-OUTS #
58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
60 | for user mode applications.
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
80 | a1 - user destination address
[all …]
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| D | CHANGES | 3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
31 ---------------------------
42 mode was pre-decrement or post-increment and the address register
49 ---------
56 -------
66 ----
70 ------
71 Upon receiving a non-zero (failing) return value from
72 a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
[all …]
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| /kernel/linux/linux-6.6/arch/m68k/ifpsp060/ |
| D | os.S | 3 |M68000 Hi-Performance Microprocessor Division
5 |Production Release P1.00 -- October 10, 1994
32 | - example "Call-Out"s required by both the ISP and FPSP.
38 | EXAMPLE CALL-OUTS #
58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
60 | for user mode applications.
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
80 | a1 - user destination address
[all …]
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| D | CHANGES | 3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
31 ---------------------------
42 mode was pre-decrement or post-increment and the address register
49 ---------
56 -------
66 ----
70 ------
71 Upon receiving a non-zero (failing) return value from
72 a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/fpsp040/ |
| D | skeleton.S | 37 | Modified for Linux-1.3.x by Jes Sorensen (jds@kom.auc.dk)
42 #include <asm/asm-offsets.h>
66 link %a6,#-LOCAL_SIZE
67 fsave -(%sp)
74 movel %sp,%sp@- | stack frame pointer argument
103 link %a6,#-LOCAL_SIZE
104 fsave -(%sp)
107 fmovel %fpsr,-(%sp)
142 link %a6,#-LOCAL_SIZE
143 fsave -(%sp)
[all …]
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| /kernel/linux/linux-6.6/arch/m68k/fpsp040/ |
| D | skeleton.S | 37 | Modified for Linux-1.3.x by Jes Sorensen (jds@kom.auc.dk)
42 #include <asm/asm-offsets.h>
66 link %a6,#-LOCAL_SIZE
67 fsave -(%sp)
74 movel %sp,%sp@- | stack frame pointer argument
103 link %a6,#-LOCAL_SIZE
104 fsave -(%sp)
107 fmovel %fpsr,-(%sp)
142 link %a6,#-LOCAL_SIZE
143 fsave -(%sp)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/book3s/32/ |
| D | mmu-hash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * 32-bit hash table MMU support
57 #define PP_RWXX 0 /* Supervisor read/write, User none */
58 #define PP_RWRX 1 /* Supervisor read/write, User read */
59 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60 #define PP_RXRX 3 /* Supervisor read, User read */
65 #define SR_KS 0x40000000 /* Supervisor key */
80 unsigned long xpn:3; /* Real page number bits 0-2, optional */
83 unsigned long w:1; /* Write-thru cache mode */
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | sl28cpld.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
17 -----------
21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
26 switch to x8 mode to support a wider input range at the loss of
30 -------------
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| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | sl28cpld.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
17 -----------
21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
26 switch to x8 mode to support a wider input range at the loss of
30 -------------
|
| /kernel/linux/linux-6.6/arch/riscv/include/asm/ |
| D | csr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
39 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
48 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
49 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
50 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
35 #define ACR_USER 0x00000000 /* User mode access only */
36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
37 #define ACR_ANY 0x00004000 /* Match any access mode */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
39 #define ACR_CM_CP 0x00000020 /* Copyback mode */
42 #define ACR_CM 0x00000060 /* Cache mode mask */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
[all …]
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| D | mcfdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfdma.h -- Coldfire internal DMA support defines.
73 #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
79 /* Bit definitions for the DMA Mode Register (DMR) */
82 #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
83 #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
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| D | mcfmmu.h | 2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
35 #define MMUCR_EN 0x00000001 /* Virtual mode enable */
36 #define MMUCR_ASM 0x00000002 /* Address space mode */
47 #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48 #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
82 #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
83 #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
35 #define ACR_USER 0x00000000 /* User mode access only */
36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
37 #define ACR_ANY 0x00004000 /* Match any access mode */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
39 #define ACR_CM_CP 0x00000020 /* Copyback mode */
42 #define ACR_CM 0x00000060 /* Cache mode mask */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
[all …]
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| D | mcfdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfdma.h -- Coldfire internal DMA support defines.
73 #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
79 /* Bit definitions for the DMA Mode Register (DMR) */
82 #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
83 #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
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| D | mcfmmu.h | 2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
35 #define MMUCR_EN 0x00000001 /* Virtual mode enable */
36 #define MMUCR_ASM 0x00000002 /* Address space mode */
47 #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48 #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
82 #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
83 #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
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| /kernel/linux/linux-5.10/arch/microblaze/include/asm/ |
| D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
12 # include <asm-generic/mmu.h>
30 unsigned long w:1; /* Write-thru cache mode */
39 # define PP_RWXX 0 /* Supervisor read/write, User none */
40 # define PP_RWRX 1 /* Supervisor read/write, User read */
41 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
42 # define PP_RXRX 3 /* Supervisor read, User read */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
[all …]
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| /kernel/linux/linux-6.6/arch/microblaze/include/asm/ |
| D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
46 unsigned long n:1; /* No-execute */
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/book3s/32/ |
| D | mmu-hash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * 32-bit hash table MMU support
57 #define PP_RWXX 0 /* Supervisor read/write, User none */
58 #define PP_RWRX 1 /* Supervisor read/write, User read */
59 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60 #define PP_RXRX 3 /* Supervisor read, User read */
65 #define SR_KS 0x40000000 /* Supervisor key */
69 #include <asm/asm-offsets.h>
147 * of the 32-bit virtual address (the "effective segment ID") in order
165 unsigned long xpn:3; /* Real page number bits 0-2, optional */
[all …]
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| /kernel/linux/linux-5.10/arch/x86/kernel/fpu/ |
| D | xstate.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 "AVX-512 opmask" ,
36 "AVX-512 Hi256" ,
37 "AVX-512 ZMM_Hi256" ,
60 * XSAVE buffer, both supervisor and user xstates.
64 static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
65 static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
66 static unsigned int xstate_comp_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
67 static unsigned int xstate_supervisor_only_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1…
71 * it is always in standard format for user mode. This is the user
[all …]
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| /kernel/linux/linux-6.6/arch/openrisc/include/asm/ |
| D | spr_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
269 #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
295 #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
[all …]
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| /kernel/linux/linux-5.10/arch/openrisc/include/asm/ |
| D | spr_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
269 #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
295 #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
[all …]
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