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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer External Interrupt Unit (EXIU)
10 - Ard Biesheuvel <ardb@kernel.org>
13 The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
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Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dsocionext,synquacer-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext SynQuacer HS-SPI Controller
10 - Masahisa Kojima <masahisa.kojima@linaro.org>
11 - Jassi Brar <jaswinder.singh@linaro.org>
14 - $ref: spi-controller.yaml#
18 const: socionext,synquacer-spi
26 - description: core clock
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsocionext,synquacer-exiu.txt1 Socionext SynQuacer External Interrupt Unit (EXIU)
3 The Socionext Synquacer SoC has an external interrupt unit (EXIU)
5 level-high type GICv3 SPIs.
9 - compatible : Should be "socionext,synquacer-exiu".
10 - reg : Specifies base physical address and size of the
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
20 - Only SPIs can use the EXIU as an interrupt parent.
24 exiu: interrupt-controller@510c0000 {
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Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-synquacer.txt1 * Socionext Synquacer HS-SPI bindings
4 - compatible: should be "socionext,synquacer-spi"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts.
8 - clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK)
9 - clock-names: Shall be "iHCLK" and "iPCLK" respectively
12 - socionext,use-rtm: boolean, if required to use "retimed clock" for RX
13 - socionext,set-aces: boolean, if same active clock edges field to be set.
17 spi0: spi@ff110000 {
18 compatible = "socionext,synquacer-spi";
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/kernel/linux/linux-5.10/drivers/char/tpm/
Dtpm_tis_synquacer.c1 // SPDX-License-Identifier: GPL-2.0
5 * This device driver implements MMIO TPM on SynQuacer Platform.
20 * irq = -1 means: no irq support
42 while (len--) in tpm_tis_synquacer_read_bytes()
43 *result++ = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
53 while (len--) in tpm_tis_synquacer_write_bytes()
54 iowrite8(*value++, phy->iobase + addr); in tpm_tis_synquacer_write_bytes()
65 * Due to the limitation of SPI controller on SynQuacer, in tpm_tis_synquacer_read16_bw()
66 * 16/32 bits access must be done in byte-wise and descending order. in tpm_tis_synquacer_read16_bw()
68 *result = (ioread8(phy->iobase + addr + 1) << 8) | in tpm_tis_synquacer_read16_bw()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 which is required to validate the PCR 0-7 values.
59 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
60 depends on SPI
64 non-tcg SPI master (i.e. most embedded platforms) that is compliant with the
71 bool "Cr50 SPI Interface"
74 If you have a H1 secure module running Cr50 firmware on SPI bus,
78 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
85 within Linux on Socionext SynQuacer platform.
90 tristate "TPM Interface Specification 1.2 Interface (I2C - Atmel)"
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/kernel/linux/linux-6.6/drivers/char/tpm/
Dtpm_tis_synquacer.c1 // SPDX-License-Identifier: GPL-2.0
5 * This device driver implements MMIO TPM on SynQuacer Platform.
19 * irq = -1 means: no irq support
43 while (len--) in tpm_tis_synquacer_read_bytes()
44 *result++ = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
47 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
48 result[0] = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
51 result[3] = ioread8(phy->iobase + addr + 3); in tpm_tis_synquacer_read_bytes()
52 result[2] = ioread8(phy->iobase + addr + 2); in tpm_tis_synquacer_read_bytes()
53 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 which is required to validate the PCR 0-7 values.
59 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
60 depends on SPI
64 non-tcg SPI master (i.e. most embedded platforms) that is compliant with the
71 bool "Cr50 SPI Interface"
74 If you have a H1 secure module running Cr50 firmware on SPI bus,
78 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
90 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
97 within Linux on Socionext SynQuacer platform.
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
3 // Synquacer HSSPI controller driver
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
19 #include <linux/spi/spi.h>
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for kernel SPI drivers.
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
16 # SPI master controller drivers (bus)
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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/kernel/linux/linux-6.6/drivers/spi/
Dspi-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
3 // Synquacer HSSPI controller driver
5 // Copyright (c) 2015-2018 Socionext Inc.
6 // Copyright (c) 2018-2019 Linaro Ltd.
19 #include <linux/spi/spi.h>
108 (SYNQUACER_HSSPI_FIFO_DEPTH - SYNQUACER_HSSPI_FIFO_TX_THRESHOLD)
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS); in read_fifo()
147 len = min(len, sspi->rx_words); in read_fifo()
149 switch (sspi->bpw) { in read_fifo()
151 u8 *buf = sspi->rx_buf; in read_fifo()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for kernel SPI drivers.
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
16 # SPI master controller drivers (bus)
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Trivial I2C and SPI devices
10 - Rob Herring <robh@kernel.org>
13 This is a list of trivial I2C and SPI devices that have simple device tree
27 spi-max-frequency: true
31 - enum:
33 - acbel,fsg032
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Trivial I2C and SPI devices that have simple device tree bindings
10 - Rob Herring <robh@kernel.org>
13 This is a list of trivial I2C and SPI devices that have simple device tree
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-sni-exiu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
69 writel_relaxed(val, data->base + EIMASK); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
79 writel_relaxed(val, data->base + EIMASK); in exiu_irq_unmask()
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/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-sni-exiu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
7 * Based on irq-tegra.c:
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_ack()
58 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
69 writel_relaxed(val, data->base + EIMASK); in exiu_irq_mask()
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
79 writel_relaxed(val, data->base + EIMASK); in exiu_irq_unmask()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
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Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/kernel/linux/linux-6.6/drivers/i2c/busses/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
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/kernel/linux/linux-5.10/drivers/i2c/busses/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 controller is part of the 7101 device, which is an ACPI-compliant
22 will be called i2c-ali1535.
30 controller is part of the 7101 device, which is an ACPI-compliant
34 will be called i2c-ali1563.
44 will be called i2c-ali15x3.
56 will be called i2c-amd756.
63 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
69 will be called i2c-amd756-s4882.
79 will be called i2c-amd8111.
[all …]

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