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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dnvidia,tegra20-slink.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20/30 SLINK controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-slink
17 - nvidia,tegra30-slink
27 - description: module clock
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dnvidia,tegra20-slink.txt1 NVIDIA Tegra20/Tegra30 SLINK controller.
4 - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
5 - reg: Should contain SLINK registers location and length.
6 - interrupts: Should contain SLINK interrupts.
7 - clocks : Must contain one entry, for the module clock.
8 See ../clocks/clock-bindings.txt for details.
9 - resets : Must contain an entry for each entry in reset-names.
11 - reset-names : Must include the following entries:
12 - spi
13 - dmas : Must contain an entry for each entry in clock-names.
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
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Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
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/kernel/linux/linux-6.6/drivers/spi/
Dspi-tegra20-slink.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
12 #include <linux/dma-mapping.h>
212 return readl(tspi->base + reg); in tegra_slink_readl()
218 writel(val, tspi->base + reg); in tegra_slink_writel()
222 readl(tspi->base + SLINK_MAS_DATA); in tegra_slink_writel()
239 switch (tspi->bytes_per_word) { in tegra_slink_get_packed_size()
257 unsigned remain_len = t->len - tspi->cur_pos; in tegra_slink_calculate_curr_xfer_param()
263 bits_per_word = t->bits_per_word; in tegra_slink_calculate_curr_xfer_param()
264 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_slink_calculate_curr_xfer_param()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
18 obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
224 this code to manage the per-word or per-transfer accesses to the
254 Flash over 1/2/4-bit wide bus. Enable this option if you have a
266 Flash over up to 8-bit wide bus. Enable this option if you have a
274 This enables dedicated general purpose SPI/Microwire1-compatible
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-tegra20-slink.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
12 #include <linux/dma-mapping.h>
213 return readl(tspi->base + reg); in tegra_slink_readl()
219 writel(val, tspi->base + reg); in tegra_slink_writel()
223 readl(tspi->base + SLINK_MAS_DATA); in tegra_slink_writel()
240 switch (tspi->bytes_per_word) { in tegra_slink_get_packed_size()
258 unsigned remain_len = t->len - tspi->cur_pos; in tegra_slink_calculate_curr_xfer_param()
264 bits_per_word = t->bits_per_word; in tegra_slink_calculate_curr_xfer_param()
265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_slink_calculate_curr_xfer_param()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
18 obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
111 supports spi-mem interface.
181 this code to manage the per-word or per-transfer accesses to the
211 Flash over 1/2/4-bit wide bus. Enable this option if you have a
219 This enables dedicated general purpose SPI/Microwire1-compatible
220 master mode interface (SSI1) for CLPS711X-based CPUs.
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