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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-stm32-usbphyc.txt14 |_ PHY port#2 ----| |________________
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
32 - resets: phandle + reset specifier
34 Required nodes: one sub-node per port the controller provides.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32mp157a-stinger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
24 stdout-path = "serial1:115200n8";
33 compatible = "gpio-leds";
38 linux,default-trigger = "heartbeat";
39 default-state = "off";
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Dstm32mp15xx-dhcom-pdk2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = "serial0:115200n8";
20 clk_ext_audio_codec: clock-codec {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
26 display_bl: display-bl {
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Dstm32mp157c-ed1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/st,stpmic1.h>
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
20 stdout-path = "serial0:115200n8";
28 reserved-memory {
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Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
33 compatible = "hdmi-connector";
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Dstm32mp15xx-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = "serial0:115200n8";
36 rs485-rx-en {
37 gpio-hog;
39 output-low;
40 line-name = "rs485-rx-en";
45 gpio-line-names = "", "", "", "",
52 gpio-line-names = "In1", "", "", "",
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Dstm32mp15xx-dkx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/mfd/st,stpmic1.h>
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "shared-dma-pool";
24 no-map;
28 compatible = "shared-dma-pool";
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/kernel/linux/linux-6.6/drivers/phy/st/
Dphy-stm32-usbphyc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
152 struct regulator *vdda1v1; member
173 ret = regulator_enable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_enable()
177 ret = regulator_enable(usbphyc->vdda1v8); in stm32_usbphyc_regulators_enable()
184 regulator_disable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_enable()
193 ret = regulator_disable(usbphyc->vdda1v8); in stm32_usbphyc_regulators_disable()
197 ret = regulator_disable(usbphyc->vdda1v1); in stm32_usbphyc_regulators_disable()
217 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16 in stm32_usbphyc_get_pll_params()
223 pll_params->ndiv = (u8)ndiv; in stm32_usbphyc_get_pll_params()
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/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstm32mp15-scmi.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
10 compatible = "linaro,optee-tz";
15 compatible = "linaro,scmi-optee";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 linaro,optee-channel-id = <0>;
22 #clock-cells = <1>;
27 #reset-cells = <1>;
34 #address-cells = <1>;
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Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/kernel/linux/linux-5.10/drivers/phy/st/
Dphy-stm32-usbphyc.c1 // SPDX-License-Identifier: GPL-2.0
40 "vdda1v1", /* 1V1 */
99 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16 in stm32_usbphyc_get_pll_params()
105 pll_params->ndiv = (u8)ndiv; in stm32_usbphyc_get_pll_params()
109 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
110 pll_params->frac = (u16)frac; in stm32_usbphyc_get_pll_params()
116 u32 clk_rate = clk_get_rate(usbphyc->clk); in stm32_usbphyc_pll_init()
122 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n", in stm32_usbphyc_pll_init()
124 return -EINVAL; in stm32_usbphyc_pll_init()
136 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); in stm32_usbphyc_pll_init()
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