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/kernel/linux/linux-6.6/sound/soc/codecs/
Dmt6359.h140 #define AUXADC_RQST_CH0_MASK 0x1
141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
172 #define RG_ACCDET_CK_PDN_MASK 0x1
173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
[all …]
Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
Drt5616.h152 #define RT5616_L_MUTE (0x1 << 15)
154 #define RT5616_VOL_L_MUTE (0x1 << 14)
156 #define RT5616_R_MUTE (0x1 << 7)
158 #define RT5616_VOL_R_MUTE (0x1 << 6)
166 #define RT5616_EN_DFO (0x1 << 15)
174 #define RT5616_IN_DF1 (0x1 << 7)
176 #define RT5616_IN_DF2 (0x1 << 6)
182 #define RT5616_INR_SEL_MASK (0x1 << 7)
185 #define RT5616_INR_SEL_MONON (0x1 << 7)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
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Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
[all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/qib/
Dqib_7220_regs.h39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
[all …]
Dqib_6120_regs.h37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
53 #define QIB_6120_Control_TxLatency_RMASK 0x1
55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
57 #define QIB_6120_Control_LinkEn_RMASK 0x1
58 #define QIB_6120_Control_FreezeMode_LSB 0x1
59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
61 #define QIB_6120_Control_SyncReset_RMASK 0x1
81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
[all …]
Dqib_7322_regs.h39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
66 #define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1
69 #define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1
72 #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1
75 #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1
76 #define QIB_7322_Control_FreezeMode_LSB 0x1
77 #define QIB_7322_Control_FreezeMode_MSB 0x1
78 #define QIB_7322_Control_FreezeMode_RMASK 0x1
81 #define QIB_7322_Control_SyncReset_RMASK 0x1
[all …]
/kernel/linux/linux-6.6/drivers/infiniband/hw/qib/
Dqib_7220_regs.h39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
[all …]
Dqib_6120_regs.h37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
53 #define QIB_6120_Control_TxLatency_RMASK 0x1
55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
57 #define QIB_6120_Control_LinkEn_RMASK 0x1
58 #define QIB_6120_Control_FreezeMode_LSB 0x1
59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
61 #define QIB_6120_Control_SyncReset_RMASK 0x1
81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
[all …]
Dqib_7322_regs.h39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
66 #define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1
69 #define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1
72 #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1
75 #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1
76 #define QIB_7322_Control_FreezeMode_LSB 0x1
77 #define QIB_7322_Control_FreezeMode_MSB 0x1
78 #define QIB_7322_Control_FreezeMode_RMASK 0x1
81 #define QIB_7322_Control_SyncReset_RMASK 0x1
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/kernel/linux/linux-6.6/sound/soc/mediatek/mt8192/
Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
Dmt6359.h140 #define RG_LDO_VAUD18_EN_MASK 0x1
141 #define RG_LDO_VAUD18_EN_MASK_SFT (0x1 << 0)
145 #define RG_VOW13M_CK_PDN_MASK 0x1
146 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
148 #define RG_VOW32K_CK_PDN_MASK 0x1
149 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
151 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
152 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
154 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
155 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
[all …]
Drt5616.h152 #define RT5616_L_MUTE (0x1 << 15)
154 #define RT5616_VOL_L_MUTE (0x1 << 14)
156 #define RT5616_R_MUTE (0x1 << 7)
158 #define RT5616_VOL_R_MUTE (0x1 << 6)
166 #define RT5616_EN_DFO (0x1 << 15)
174 #define RT5616_IN_DF1 (0x1 << 7)
176 #define RT5616_IN_DF2 (0x1 << 6)
182 #define RT5616_INR_SEL_MASK (0x1 << 7)
185 #define RT5616_INR_SEL_MONON (0x1 << 7)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
[all …]
Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
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Drt5645.h219 #define RT5645_L_MUTE (0x1 << 15)
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
223 #define RT5645_R_MUTE (0x1 << 7)
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
235 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
239 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
240 #define RT5645_CBJ_MIC_SW (0x1 << 4)
[all …]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt6797/
Dmt6797-reg.h263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 25)
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt6797/
Dmt6797-reg.h263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 25)
[all …]
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8183/
Dmt8183-reg.h418 #define BCK_INVERSE_MASK 0x1
419 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
423 #define AWB2_ON_MASK 0x1
424 #define AWB2_ON_MASK_SFT (0x1 << 29)
426 #define VUL2_ON_MASK 0x1
427 #define VUL2_ON_MASK_SFT (0x1 << 27)
429 #define MOD_DAI_DUP_WR_MASK 0x1
430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
435 #define VUL12_R_MONO_MASK 0x1
436 #define VUL12_R_MONO_MASK_SFT (0x1 << 11)
[all …]
/kernel/linux/linux-5.10/sound/soc/mediatek/mt8183/
Dmt8183-reg.h418 #define BCK_INVERSE_MASK 0x1
419 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
423 #define AWB2_ON_MASK 0x1
424 #define AWB2_ON_MASK_SFT (0x1 << 29)
426 #define VUL2_ON_MASK 0x1
427 #define VUL2_ON_MASK_SFT (0x1 << 27)
429 #define MOD_DAI_DUP_WR_MASK 0x1
430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
435 #define VUL12_R_MONO_MASK 0x1
436 #define VUL12_R_MONO_MASK_SFT (0x1 << 11)
[all …]
/kernel/linux/linux-5.10/drivers/soc/samsung/
Dexynos3250-pmu.c21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
30 { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
31 { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
32 { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
33 { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
34 { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
[all …]
Dexynos4-pmu.c24 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
25 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
26 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
27 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
28 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
29 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
30 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
31 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
32 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
33 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
[all …]
/kernel/linux/linux-6.6/drivers/soc/samsung/
Dexynos3250-pmu.c21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
30 { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
31 { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
32 { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
33 { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
34 { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
[all …]
Dexynos4-pmu.c24 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
25 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
26 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
27 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
28 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
29 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
30 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
31 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
32 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
33 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/qed/
Dqed_hsi.h322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
326 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
342 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
[all …]

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