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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/
Dxilinx_can.txt1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx Axi CAN/Zynq CANPS controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
[all …]
Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-…
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dxilinx-xadc.txt6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
16 communication. Xilinx provides a standard IP core that can be used to access the
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dxilinx-xadc.txt4 bindings are very similar. The Xilinx XADC is a ADC that can be found in the
7 available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
13 - compatible: Should be one of
14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
16 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
18 - reg: Address and length of the register set for the device
19 - interrupts: Interrupt for the XADC control interface.
20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
21 when using the AXI-XADC pcore this must be the clock that provides the
25 - xlnx,external-mux:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynq-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
21 parameters, such as pull-up, slew rate, etc.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynq-pinctrl.txt1 Binding for Xilinx Zynq Pinctrl
4 - compatible: "xlnx,zynq-pinctrl"
5 - syscon: phandle to SLCR
6 - reg: Offset and length of pinctrl space in SLCR
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Zynq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
16 parameters, such as pull-up, slew rate, etc.
18 Each configuration node can consist of multiple nodes describing the pinmux and
19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-zynq/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk/zynq.h>
24 #include <linux/irqchip/arm-gic.h>
32 #include <asm/mach-types.h>
36 #include <asm/hardware/cache-l2x0.h>
47 * zynq_memory_init - Initialize special memory
49 * We need to stop things allocating the low memory as DMA can't work in
50 * the 1st 512K of memory.
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
[all …]
Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
13 #include <linux/clk/zynq.h>
34 * zynq_slcr_write - Write to a register in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
72 * zynq_slcr_get_device_id - Read device code id
88 * zynq_slcr_system_restart - Restart the entire system.
104 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
109 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); in zynq_slcr_system_restart()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-zynq/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk/zynq.h>
24 #include <linux/irqchip/arm-gic.h>
32 #include <asm/mach-types.h>
36 #include <asm/hardware/cache-l2x0.h>
47 * zynq_memory_init - Initialize special memory
49 * We need to stop things allocating the low memory as DMA can't work in
50 * the 1st 512K of memory.
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
[all …]
Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
13 #include <linux/clk/zynq.h>
34 * zynq_slcr_write - Write to a register in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
72 * zynq_slcr_get_device_id - Read device code id
88 * zynq_slcr_system_restart - Restart the entire system.
104 * the FSBL not loading the bitstream after soft-reboot in zynq_slcr_system_restart()
109 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); in zynq_slcr_system_restart()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/kernel/linux/linux-6.6/Documentation/networking/device_drivers/can/ctu/
Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 CTU CAN FD Driver
9 About CTU CAN FD IP Core
10 ------------------------
12 `CTU CAN FD <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
18 The SocketCAN driver for Xilinx Zynq SoC based MicroZed board
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
[all …]
/kernel/linux/linux-6.6/drivers/fpga/
Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER 1
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
[all …]
/kernel/linux/linux-5.10/drivers/fpga/
Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER 1
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
[all …]
/kernel/linux/linux-6.6/drivers/clk/zynq/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
35 #define PLLCTRL_BPQUAL_MASK (1 << 3)
37 #define PLLCTRL_PWRDWN_SHIFT 1
38 #define PLLCTRL_RESET_MASK 1
45 * zynq_pll_round_rate() - Round a clock frequency
[all …]
/kernel/linux/linux-5.10/drivers/clk/zynq/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
9 #include <linux/clk/zynq.h>
10 #include <linux/clk-provider.h>
16 * @hw: Handle between common and hardware-specific interfaces
35 #define PLLCTRL_BPQUAL_MASK (1 << 3)
37 #define PLLCTRL_PWRDWN_SHIFT 1
38 #define PLLCTRL_RESET_MASK 1
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
[all …]
/kernel/linux/linux-5.10/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 protocol. Chips that support SPI can have data transfer rates
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
44 If your system has an master-capable SPI controller (which
45 provides the clock and chipselect), you can enable that
56 by providing a high-level interface to send memory-like commands.
111 supports spi-mem interface.
178 With a few GPIO pins, your system can bitbang the SPI protocol.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nvidia,tegra20-ehci
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
[all …]
/kernel/linux/linux-5.10/drivers/iio/adc/
Dxilinx-xadc-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
35 #include "xilinx-xadc.h"
39 /* ZYNQ register definitions */
107 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
[all …]
/kernel/linux/linux-6.6/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 protocol. Chips that support SPI can have data transfer rates
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
44 If your system has an master-capable SPI controller (which
45 provides the clock and chipselect), you can enable that
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
221 With a few GPIO pins, your system can bitbang the SPI protocol.
[all …]
/kernel/linux/linux-6.6/drivers/iio/adc/
Dxilinx-xadc-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
36 #include "xilinx-xadc.h"
40 /* ZYNQ register definitions */
111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
[all …]

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