1 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
2 /*
3 *
4 * (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
5 *
6 * This program is free software and is provided to you under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation, and any use by you of this program is subject to the terms
9 * of such GNU license.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you can access it online at
18 * http://www.gnu.org/licenses/gpl-2.0.html.
19 *
20 */
21
22 #include <mali_kbase.h>
23 #include <gpu/mali_kbase_gpu_fault.h>
24 #include <backend/gpu/mali_kbase_instr_internal.h>
25 #include <backend/gpu/mali_kbase_pm_internal.h>
26 #include <device/mali_kbase_device.h>
27 #include <mali_kbase_reset_gpu.h>
28 #include <mmu/mali_kbase_mmu.h>
29 #include <mali_kbase_ctx_sched.h>
30
31 /**
32 * kbase_report_gpu_fault - Report a GPU fault of the device.
33 *
34 * @kbdev: Kbase device pointer
35 * @status: Fault status
36 * @as_nr: Faulty address space
37 * @as_valid: true if address space is valid
38 *
39 * This function is called from the interrupt handler when a GPU fault occurs.
40 */
kbase_report_gpu_fault(struct kbase_device * kbdev,u32 status,u32 as_nr,bool as_valid)41 static void kbase_report_gpu_fault(struct kbase_device *kbdev, u32 status,
42 u32 as_nr, bool as_valid)
43 {
44 u64 address = (u64) kbase_reg_read(kbdev,
45 GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32;
46
47 address |= kbase_reg_read(kbdev,
48 GPU_CONTROL_REG(GPU_FAULTADDRESS_LO));
49
50 /* Report GPU fault for all contexts in case either
51 * the address space is invalid or it's MCU address space.
52 */
53 kbase_mmu_gpu_fault_interrupt(kbdev, status, as_nr, address, as_valid);
54 }
55
kbase_gpu_fault_interrupt(struct kbase_device * kbdev)56 static void kbase_gpu_fault_interrupt(struct kbase_device *kbdev)
57 {
58 const u32 status = kbase_reg_read(kbdev,
59 GPU_CONTROL_REG(GPU_FAULTSTATUS));
60 const bool as_valid = status & GPU_FAULTSTATUS_JASID_VALID_FLAG;
61 const u32 as_nr = (status & GPU_FAULTSTATUS_JASID_MASK) >>
62 GPU_FAULTSTATUS_JASID_SHIFT;
63 bool bus_fault = (status & GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) ==
64 GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_BUS_FAULT;
65
66 if (bus_fault) {
67 /* If as_valid, reset gpu when ASID is for MCU. */
68 if (!as_valid || (as_nr == MCU_AS_NR)) {
69 kbase_report_gpu_fault(kbdev, status, as_nr, as_valid);
70
71 dev_err(kbdev->dev, "GPU bus fault triggering gpu-reset ...\n");
72 if (kbase_prepare_to_reset_gpu(
73 kbdev, RESET_FLAGS_HWC_UNRECOVERABLE_ERROR))
74 kbase_reset_gpu(kbdev);
75 } else {
76 /* Handle Bus fault */
77 if (kbase_mmu_bus_fault_interrupt(kbdev, status, as_nr))
78 dev_warn(kbdev->dev,
79 "fail to handle GPU bus fault ...\n");
80 }
81 } else
82 kbase_report_gpu_fault(kbdev, status, as_nr, as_valid);
83
84 }
85
kbase_gpu_interrupt(struct kbase_device * kbdev,u32 val)86 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
87 {
88 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ, NULL, val);
89 if (val & GPU_FAULT)
90 kbase_gpu_fault_interrupt(kbdev);
91
92 if (val & GPU_PROTECTED_FAULT) {
93 struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
94 unsigned long flags;
95
96 dev_err_ratelimited(kbdev->dev, "GPU fault in protected mode");
97
98 /* Mask the protected fault interrupt to avoid the potential
99 * deluge of such interrupts. It will be unmasked on GPU reset.
100 */
101 spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
102 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK),
103 GPU_IRQ_REG_ALL & ~GPU_PROTECTED_FAULT);
104 spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
105
106 kbase_csf_scheduler_spin_lock(kbdev, &flags);
107 if (!WARN_ON(!kbase_csf_scheduler_protected_mode_in_use(
108 kbdev))) {
109 struct base_gpu_queue_group_error const
110 err_payload = { .error_type =
111 BASE_GPU_QUEUE_GROUP_ERROR_FATAL,
112 .payload = {
113 .fatal_group = {
114 .status =
115 GPU_EXCEPTION_TYPE_SW_FAULT_0,
116 } } };
117
118 scheduler->active_protm_grp->faulted = true;
119 kbase_csf_add_group_fatal_error(
120 scheduler->active_protm_grp, &err_payload);
121 kbase_event_wakeup(scheduler->active_protm_grp->kctx);
122 }
123 kbase_csf_scheduler_spin_unlock(kbdev, flags);
124
125 if (kbase_prepare_to_reset_gpu(
126 kbdev, RESET_FLAGS_HWC_UNRECOVERABLE_ERROR))
127 kbase_reset_gpu(kbdev);
128
129 /* Defer the clearing to the GPU reset sequence */
130 val &= ~GPU_PROTECTED_FAULT;
131 }
132
133 if (val & RESET_COMPLETED)
134 kbase_pm_reset_done(kbdev);
135
136 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val);
137 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val);
138
139 #ifdef KBASE_PM_RUNTIME
140 if (val & DOORBELL_MIRROR) {
141 unsigned long flags;
142
143 dev_dbg(kbdev->dev, "Doorbell mirror interrupt received");
144 spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
145 WARN_ON(!kbase_csf_scheduler_get_nr_active_csgs(kbdev));
146 kbase_pm_disable_db_mirror_interrupt(kbdev);
147 kbdev->pm.backend.exit_gpu_sleep_mode = true;
148 kbase_csf_scheduler_invoke_tick(kbdev);
149 spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
150 }
151 #endif
152
153 /* kbase_pm_check_transitions (called by kbase_pm_power_changed) must
154 * be called after the IRQ has been cleared. This is because it might
155 * trigger further power transitions and we don't want to miss the
156 * interrupt raised to notify us that these further transitions have
157 * finished. The same applies to kbase_clean_caches_done() - if another
158 * clean was queued, it might trigger another clean, which might
159 * generate another interrupt which shouldn't be missed.
160 */
161
162 if (val & CLEAN_CACHES_COMPLETED)
163 kbase_clean_caches_done(kbdev);
164
165 if (val & (POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ)) {
166 kbase_pm_power_changed(kbdev);
167 } else if (val & CLEAN_CACHES_COMPLETED) {
168 /* If cache line evict messages can be lost when shader cores
169 * power down then we need to flush the L2 cache before powering
170 * down cores. When the flush completes, the shaders' state
171 * machine needs to be re-invoked to proceed with powering down
172 * cores.
173 */
174 if (kbdev->pm.backend.l2_always_on ||
175 kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TTRX_921))
176 kbase_pm_power_changed(kbdev);
177 }
178
179 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
180 }
181
182 #if !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
kbase_is_register_accessible(u32 offset)183 static bool kbase_is_register_accessible(u32 offset)
184 {
185 #ifdef CONFIG_MALI_BIFROST_DEBUG
186 if (((offset >= MCU_SUBSYSTEM_BASE) && (offset < IPA_CONTROL_BASE)) ||
187 ((offset >= GPU_CONTROL_MCU_BASE) && (offset < USER_BASE))) {
188 WARN(1, "Invalid register offset 0x%x", offset);
189 return false;
190 }
191 #endif
192
193 return true;
194 }
195
kbase_reg_write(struct kbase_device * kbdev,u32 offset,u32 value)196 void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
197 {
198 KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
199 KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
200
201 if (!kbase_is_register_accessible(offset))
202 return;
203
204 writel(value, kbdev->reg + offset);
205
206 #if IS_ENABLED(CONFIG_DEBUG_FS)
207 if (unlikely(kbdev->io_history.enabled))
208 kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
209 value, 1);
210 #endif /* CONFIG_DEBUG_FS */
211 dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
212 }
213 KBASE_EXPORT_TEST_API(kbase_reg_write);
214
kbase_reg_read(struct kbase_device * kbdev,u32 offset)215 u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
216 {
217 u32 val;
218
219 KBASE_DEBUG_ASSERT(kbdev->pm.backend.gpu_powered);
220 KBASE_DEBUG_ASSERT(kbdev->dev != NULL);
221
222 if (!kbase_is_register_accessible(offset))
223 return 0;
224
225 val = readl(kbdev->reg + offset);
226
227 #if IS_ENABLED(CONFIG_DEBUG_FS)
228 if (unlikely(kbdev->io_history.enabled))
229 kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
230 val, 0);
231 #endif /* CONFIG_DEBUG_FS */
232 dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
233
234 return val;
235 }
236 KBASE_EXPORT_TEST_API(kbase_reg_read);
237 #endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
238