1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "hdmi_hal_phy.h"
20 #include "hdmi_reg_dphy.h"
21 #include "hdmi_product_define.h"
22 #include "hdmi_reg_tx.h"
23 #include "hdmi_hal_intf.h"
24 #include "drv_hdmi_common.h"
25
26 #define PHY_LOOP_DIV_CFG_25 0x640000 /* 25 x 4 = 100 = 0x64 */
27 #define PHY_LOOP_DIV_CFG_22 0x5a0000 /* 22 x 4 = 90 = 0x5a */
28 #define PHY_FEEDTHRU_EN_MASK (0x1 << 2)
29 #define PHY_FEEDTHRU_DATA_MASK 0x3
30 #define PHY_HWSPEC_I_16 16
31 #define PHY_HWSPEC_I_28 28
32 #define PHY_HWSPEC_I_32 32
33 #define PHY_HWSPEC_I_MAX 43
34 #define PHY_RATIO_1_10_MASK 0x1f /* 10bit/2 eq 1 */
35 #define PHY_RATIO_1_40_MASK 0xfffff /* 40bit/2 eq 1 */
36 #define PHY_TXPLL_TEST_OFF 0
37 #define PHY_TXPLL_TEST_ON 0x30000
38 #define PHY_POWER_ON_MASK_CLK 0xe
39 #define PHY_POWER_ON_MASK_D0 0xd
40 #define PHY_POWER_ON_MASK_D1 0xb
41 #define PHY_POWER_ON_MASK_D2 0x7
42 #define PHY_POWER_OFF 0xf
43 #define PHY_POWER_ON 0
44 #define PHY_POWER_LDO_OFF 0x3
45 #define PHY_OE_OFF 0xf
46 #define PHY_OE_ON 0
47 #define PHY_I_CHARGE_PUMP 0x3
48 #define PHY_PLL_LOOP_DEVIDER 0x20
49 #define TMDS_CLOCK_25M 25000
50 #define TMDS_CLOCK_100M 100000
51 #define TMDS_CLOCK_165M 165000
52 #define TMDS_CLOCK_340M 340000
53 #define HDMI_HW_PARAM_NUM 4
54
55 typedef enum {
56 PHY_CLK_RATIO_1_10,
57 PHY_CLK_RATIO_1_40
58 } phy_clk_ratio;
59
60 typedef enum {
61 INTERPOLATION_MODE_1X,
62 INTERPOLATION_MODE_2X,
63 INTERPOLATION_MODE_4X,
64 INTERPOLATION_MODE_8X,
65 INTERPOLATION_MODE_BUTT
66 } phy_div_mode;
67
68 typedef struct {
69 phy_rterm_mode r_term_mode;
70 hi_u32 mode_data_clk;
71 hi_u32 mode_data_d0;
72 hi_u32 mode_data_d1;
73 hi_u32 mode_data_d2;
74 } phy_rterm_mode_data;
75
76 typedef struct {
77 hi_u32 phy_gc_ldo_pd;
78 hi_u32 phy_gc_de_pd;
79 hi_bool phy_gc_bist_pd;
80 hi_bool phy_gc_txpll_pd;
81 hi_bool phy_gc_rxsense_pd;
82 } phy_power_cfg;
83
84 typedef struct {
85 hi_u32 clk_min;
86 hi_u32 clk_max;
87 } phy_clk_range;
88
89 typedef struct {
90 phy_clk_range phy_tmds_clk_range;
91 phy_hw_spec_cfg phy_spec_cfg;
92 } phy_hw_spec;
93
94 typedef struct {
95 phy_clk_range range;
96 phy_hwspec_enhance_cfg cfg;
97 } phy_hwspec_enhance;
98
99 typedef struct {
100 phy_clk_range phy_tmds_clk_range;
101 phy_ssc_cfg ssc_cfg;
102 } phy_ssc;
103
104 typedef struct {
105 phy_clk_range pix_clk_range;
106 hdmi_deep_color deep_color;
107 hi_u32 pixel_clk_div;
108 hi_u32 ssc_byp_div;
109 hi_u32 tmds_nxdiv;
110 hi_u32 loop_div;
111 phy_clk_ratio clk_ratio;
112 phy_div_mode div_mode;
113 } phy_div_cfg;
114
115 static hdmi_phy_info g_hdmi_phy_info;
116
117 static phy_rterm_mode_data g_phy_rterm_mode_deta[] = {
118 /* R term mode clk d0 d1 d2 */
119 { PHY_RTERM_MODE_SINGLE, 0x03, 0x0c, 0x30, 0xc0 },
120 { PHY_RTERM_MODE_SOURCE, 0x02, 0x08, 0x20, 0x80 },
121 { PHY_RTERM_MODE_LOAD, 0x01, 0x04, 0x10, 0x40 },
122 { PHY_RTERM_MODE_DOUBLEDIFF, 0x00, 0x00, 0x00, 0x00 }
123 };
124
125 #ifdef PHY_CRAFT_S28
126 /* 1.0 inch */
127 static phy_hwspec_enhance g_phy_hw_spec_enhance_1p0[] = {
128 {{ 25000, 100000 },
129 { 0, 0, 0, 0, 20, 25, 25, 25,
130 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
131 PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35,
132 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
133 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
134 },
135 {{ 100001, 165000 },
136 { 0, 0, 0, 0, 20, 25, 25, 25,
137 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
138 PHY_FEEDTHRU_CAP_DELAY_45, PHY_FEEDTHRU_CAP_DELAY_45, PHY_FEEDTHRU_CAP_DELAY_45, PHY_FEEDTHRU_CAP_DELAY_45,
139 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
140 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
141 },
142 {{ 165001, 340000 },
143 { 0, 0, 0, 0, 20, 26, 26, 26,
144 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
145 PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
146 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
147 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
148 },
149 {{ 340001, 600000 },
150 { 0, 0, 0, 0, 20, 30, 30, 30,
151 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
152 PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35, PHY_FEEDTHRU_CAP_DELAY_35,
153 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
154 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
155 }
156 };
157
158 /* 1.5 inch */
159 static phy_hwspec_enhance g_phy_hw_spec_enhance_1p5[] = {
160 {{ 25000, 100000 },
161 { 0, 0, 0, 0, 20, 25, 25, 25,
162 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
163 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
164 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
165 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
166 },
167 {{ 100001, 165000 },
168 { 0, 0, 0, 0, 20, 25, 25, 25,
169 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
170 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
171 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
172 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
173 },
174 {{ 165001, 340000 },
175 { 0, 0, 0, 0, 20, 26, 26, 26,
176 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
177 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
178 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
179 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
180 },
181 {{ 340001, 600000 },
182 { 0, 0, 0, 0, 21, 31, 31, 31,
183 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
184 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
185 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
186 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
187 }
188 };
189
190 /* 2.0 inch */
191 static phy_hwspec_enhance g_phy_hw_spec_enhance_2p0[] = {
192 {{ 25000, 100000 },
193 { 0, 0, 0, 0, 20, 25, 25, 25,
194 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
195 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
196 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
197 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
198 },
199 {{ 100001, 165000 },
200 { 0, 0, 0, 0, 20, 25, 25, 25,
201 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
202 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
203 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
204 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
205 },
206 {{ 165001, 340000 },
207 { 0, 1, 1, 1, 20, 27, 27, 27,
208 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
209 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
210 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
211 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
212 },
213 {{ 340001, 600000 },
214 { 0, 0, 0, 0, 21, 31, 31, 31,
215 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
216 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
217 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
218 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
219 }
220 };
221
222 /* 2.5 inch */
223 static phy_hwspec_enhance g_phy_hw_spec_enhance_2p5[] = {
224 {{ 25000, 100000 },
225 { 0, 0, 0, 0, 20, 25, 25, 25,
226 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
227 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
228 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
229 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
230 },
231 {{ 100001, 165000 },
232 { 0, 0, 0, 0, 20, 25, 25, 25,
233 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
234 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
235 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
236 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
237 },
238 {{ 165001, 340000 },
239 { 0, 0, 0, 0, 20, 27, 27, 27,
240 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
241 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
242 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
243 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
244 },
245 {{ 340001, 600000 },
246 { 0, 0, 0, 0, 21, 32, 32, 32,
247 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
248 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
249 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
250 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
251 }
252 };
253
254 /* 3.0 inch */
255 static phy_hwspec_enhance g_phy_hw_spec_enhance_3p0[] = {
256 {{ 25000, 100000 },
257 { 0, 0, 0, 0, 20, 25, 25, 25,
258 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
259 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
260 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
261 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
262 },
263 {{ 100001, 165000 },
264 { 0, 0, 0, 0, 20, 25, 25, 25,
265 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
266 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
267 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
268 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
269 },
270 {{ 165001, 340000 },
271 { 0, 0, 0, 0, 20, 27, 27, 27,
272 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
273 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
274 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
275 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
276 },
277 {{ 340001, 600000 },
278 { 0, 0, 0, 0, 21, 32, 32, 32,
279 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
280 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
281 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
282 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
283 }
284 };
285
286 /* 3.5 inch */
287 static phy_hwspec_enhance g_phy_hw_spec_enhance_3p5[] = {
288 {{ 25000, 100000 },
289 { 0, 0, 0, 0, 20, 25, 25, 25,
290 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
291 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
292 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
293 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
294 },
295 {{ 100001, 165000 },
296 { 0, 0, 0, 0, 20, 25, 25, 25,
297 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
298 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
299 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
300 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
301 },
302 {{ 165001, 340000 },
303 { 0, 1, 1, 1, 20, 27, 27, 27,
304 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
305 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
306 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
307 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
308 },
309 {{ 340001, 600000 },
310 { 0, 1, 1, 1, 22, 33, 33, 33,
311 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
312 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
313 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
314 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
315 }
316 };
317
318 /* 4.0 inch */
319 static phy_hwspec_enhance g_phy_hw_spec_enhance_4p0[] = {
320 {{ 25000, 100000 },
321 { 0, 0, 0, 0, 20, 25, 25, 25,
322 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
323 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
324 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
325 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
326 },
327 {{ 100001, 165000 },
328 { 0, 0, 0, 0, 20, 25, 25, 25,
329 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
330 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
331 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
332 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
333 },
334 {{ 165001, 340000 },
335 { 0, 1, 1, 1, 20, 28, 28, 28,
336 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
337 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
338 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
339 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
340 },
341 {{ 340001, 600000 },
342 { 0, 1, 1, 1, 22, 33, 33, 33,
343 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
344 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
345 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
346 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
347 }
348 };
349
350 /* 4.5 inch */
351 static phy_hwspec_enhance g_phy_hw_spec_enhance_4p5[] = {
352 {{ 25000, 100000 },
353 { 0, 0, 0, 0, 20, 25, 25, 25,
354 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
355 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
356 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
357 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
358 },
359 {{ 100001, 165000 },
360 { 0, 0, 0, 0, 20, 25, 25, 25,
361 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
362 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
363 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
364 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
365 },
366 {{ 165001, 340000 },
367 { 0, 2, 2, 2, 20, 28, 28, 28,
368 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
369 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
370 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
371 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
372 },
373 {{ 340001, 600000 },
374 { 0, 2, 2, 2, 22, 34, 34, 34,
375 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
376 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
377 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
378 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
379 }
380 };
381
382 /* 5.0 inch */
383 static phy_hwspec_enhance g_phy_hw_spec_enhance_5p0[] = {
384 {{ 25000, 100000 },
385 { 0, 0, 0, 0, 20, 25, 25, 25,
386 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
387 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
388 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
389 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
390 },
391 {{ 100001, 165000 },
392 { 0, 0, 0, 0, 20, 25, 25, 25,
393 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
394 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
395 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
396 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
397 },
398 {{ 165001, 340000 },
399 { 0, 2, 2, 2, 20, 28, 28, 28,
400 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
401 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
402 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
403 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
404 },
405 {{ 340001, 600000 },
406 { 0, 2, 2, 2, 22, 34, 34, 34,
407 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
408 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
409 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
410 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
411 }
412 };
413 #endif
414
415 /*
416 * |-tmdsclk_range---|
417 * | min max |
418 * |---de_main----||-i_main/0.5m_a--||---de_pre---- ||-i_pre/0.25m_a--|
419 * | clk d0 d1 d2 || clk d0 d1 d2 || clk d0 d1 d2 || clk d0 d1 d2 |
420 * |---de_r_pre/ohm---||---r_pre/ohm---|
421 * | clk d0 d1 d2 || clk d0 d1 d2 |
422 * |---------------------------------------------r_term-------------------------------------------|
423 * | clk_rterm_mode clk_rterm d0_rterm_mode d0_rterm d1_rterm_mode d1_rterm d2_rterm_mode d2_rterm|
424 */
425 #if defined(CHIP_TYPE_hi3531dv200)
426 /* default 2.5 inch */
427 static phy_hwspec_enhance g_phy_hw_spec_enhance[] = {
428 {{ 25000, 100000 },
429 { 0, 0, 0, 0, 20, 26, 26, 26,
430 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
431 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
432 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
433 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
434 },
435 {{ 100001, 165000 },
436 { 0, 0, 0, 0, 20, 26, 26, 26,
437 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
438 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
439 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
440 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
441 },
442 {{ 165001, 340000 },
443 { 0, 0, 0, 0, 20, 27, 27, 27,
444 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
445 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
446 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
447 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
448 },
449 {{ 340001, 600000 },
450 { 0, 0, 0, 0, 21, 32, 32, 32,
451 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
452 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
453 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
454 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
455 }
456 };
457 #elif defined(CHIP_TYPE_hi3535av100)
458 /* default 3.5 inch */
459 static phy_hwspec_enhance g_phy_hw_spec_enhance[] = {
460 {{ 25000, 100000 },
461 { 0, 0, 0, 0, 20, 26, 26, 26,
462 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
463 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
464 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
465 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
466 },
467 {{ 100001, 165000 },
468 { 0, 0, 0, 0, 20, 26, 26, 26,
469 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
470 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
471 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
472 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
473 },
474 {{ 165001, 340000 },
475 { 0, 0, 0, 0, 20, 27, 27, 27,
476 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
477 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
478 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
479 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
480 },
481 {{ 340001, 600000 },
482 { 0, 1, 1, 1, 22, 33, 33, 33,
483 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
484 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
485 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
486 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
487 }
488 };
489 #elif defined(CHIP_TYPE_hi3521dv200)
490 /* default 2.5 inch */
491 static phy_hwspec_enhance g_phy_hw_spec_enhance[] = {
492 {{ 25000, 100000 },
493 { 0, 0, 0, 0, 20, 26, 26, 26,
494 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
495 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
496 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
497 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
498 },
499 {{ 100001, 165000 },
500 { 0, 0, 0, 0, 20, 26, 26, 26,
501 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
502 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
503 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
504 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, 0x50 }
505 },
506 {{ 165001, 340000 },
507 { 0, 0, 0, 0, 20, 27, 27, 27,
508 HI_FALSE, HI_TRUE, HI_TRUE, HI_TRUE,
509 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55, PHY_FEEDTHRU_CAP_DELAY_55,
510 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x30, PHY_RTERM_MODE_DOUBLEDIFF, 0x30,
511 PHY_RTERM_MODE_DOUBLEDIFF, 0x30, 0x50 }
512 },
513 {{ 340001, 600000 },
514 { 0, 0, 0, 0, 21, 32, 32, 32,
515 HI_FALSE, HI_FALSE, HI_FALSE, HI_FALSE,
516 PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18, PHY_FEEDTHRU_CAP_DELAY_18,
517 PHY_RTERM_MODE_LOAD, 0x60, PHY_RTERM_MODE_LOAD, 0x70, PHY_RTERM_MODE_LOAD, 0x70,
518 PHY_RTERM_MODE_LOAD, 0x70, 0x50 }
519 }
520 };
521 #elif defined(CHIP_TYPE_hi3516cv500)
522 #ifndef PHY_SPEC_DEBUG
523 /* 2 inch */
524 static phy_hw_spec g_phy_hw_spec[] = {
525 {{ 25000, 100000 },
526 { 0, 0, 0, 0, 22, 30, 30, 30, 0, 0, 0, 0, 20, 20, 20, 20,
527 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
528 PHY_RTERM_MODE_LOAD, 0x00, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
529 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20 }
530 },
531 {{ 100001, 165000 },
532 { 0, 0, 0, 0, 18, 26, 26, 27, 0, 0, 0, 0, 24, 24, 24, 24,
533 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
534 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x60,
535 PHY_RTERM_MODE_DOUBLEDIFF, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x60 }
536 },
537 {{ 165001, 340000 },
538 { 0, 0, 0, 0, 18, 29, 29, 29, 0, 32, 32, 32, 20, 32, 32, 32,
539 PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50,
540 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x60,
541 PHY_RTERM_MODE_DOUBLEDIFF, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x60 }
542 },
543 {{ 340001, 600000 },
544 { 5, 5, 5, 5, 29, 43, 43, 43, 0, 25, 25, 25, 20, 20, 20, 20,
545 PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
546 PHY_RTERM_MODE_SOURCE, 0x00, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80 }
547 }
548 };
549
550 /* 3 inch */
551 static phy_hw_spec g_phy_hw_spec1[] = {
552 {{ 25000, 100000 },
553 { 0, 0, 0, 0, 22, 30, 30, 31, 0, 0, 0, 0, 20, 20, 20, 20,
554 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
555 PHY_RTERM_MODE_LOAD, 0x00, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
556 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20 }
557 },
558 {{ 100001, 165000 },
559 { 0, 0, 0, 0, 18, 26, 26, 27, 0, 0, 0, 0, 24, 24, 24, 24,
560 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
561 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x60,
562 PHY_RTERM_MODE_DOUBLEDIFF, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x60 }
563 },
564 {{ 165001, 340000 },
565 { 0, 0, 0, 0, 18, 29, 29, 30, 0, 32, 32, 32, 20, 32, 32, 32,
566 PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50,
567 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x60,
568 PHY_RTERM_MODE_DOUBLEDIFF, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x60 }
569 },
570 {{ 340001, 600000 },
571 { 5, 5, 5, 5, 29, 43, 43, 43, 0, 25, 25, 25, 20, 20, 20, 20,
572 PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
573 PHY_RTERM_MODE_SOURCE, 0x00, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80 }
574 }
575 };
576
577 /* 5 inch */
578 static phy_hw_spec g_phy_hw_spec2[] = {
579 {{ 25000, 100000 },
580 { 0, 0, 0, 0, 22, 30, 30, 30, 0, 0, 0, 0, 20, 20, 20, 20,
581 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
582 PHY_RTERM_MODE_LOAD, 0x00, PHY_RTERM_MODE_DOUBLEDIFF, 0x20,
583 PHY_RTERM_MODE_DOUBLEDIFF, 0x20, PHY_RTERM_MODE_DOUBLEDIFF, 0x20 }
584 },
585 {{ 100001, 165000 },
586 { 0, 0, 0, 0, 18, 26, 26, 27, 0, 0, 0, 0, 24, 24, 24, 24,
587 PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
588 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x60,
589 PHY_RTERM_MODE_DOUBLEDIFF, 0x60, PHY_RTERM_MODE_DOUBLEDIFF, 0x60 }
590 },
591 {{ 165001, 340000 },
592 { 0, 4, 4, 4, 18, 26, 26, 27, 0, 32, 32, 32, 20, 32, 32, 32,
593 PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50,
594 PHY_RTERM_MODE_LOAD, 0x03, PHY_RTERM_MODE_DOUBLEDIFF, 0x04,
595 PHY_RTERM_MODE_DOUBLEDIFF, 0x04, PHY_RTERM_MODE_DOUBLEDIFF, 0x04 }
596 },
597 {{ 340001, 600000 },
598 { 5, 5, 5, 5, 29, 43, 43, 43, 0, 25, 25, 25, 20, 20, 20, 20,
599 PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_50, PHY_RPRE_83, PHY_RPRE_83, PHY_RPRE_83,
600 PHY_RTERM_MODE_SOURCE, 0x00, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80, PHY_RTERM_MODE_LOAD, 0x80 }
601 }
602 };
603 #endif
604 #endif
605
606 /* spread spectrum ctrl(ssc) */
607 static phy_ssc g_phy_ssc_cfg[] = {
608 {{ 25000, 70000 }, { 0, 0 }}, // 0ppm
609 {{ 70001, 90000 }, { 33, 45000 }}, // 0.33% eq 3300ppm
610 {{ 90001, 110000 }, { 25, 45000 }}, // 0.25%
611 {{ 110001, 145000 }, { 20, 45000 }}, // 0.20%
612 {{ 145001, 180000 }, { 12, 45000 }}, // 0.12%
613 {{ 180001, 220000 }, { 10, 45000 }}, // 0.10%
614 {{ 220001, 250000 }, { 8, 45000 }}, // 0.8%
615 {{ 250001, 300000 }, { 4, 45000 }}, // 0.4%
616 {{ 300001, 600000 }, { 0, 0 }} // 0
617 };
618
619 /*
620 * |-tmdsclk_range---|
621 * | min max |
622 * | deepcolor -- pix_div -- byp_div -- tmds_nx_div -- loopdiv -- clk_ratio -- phy_div_mode
623 */
624 static phy_div_cfg g_phy_div_cfg[] = {
625 {{ 25000, 50000 },
626 HDMI_DEEP_COLOR_24BIT, 16, 10, 8, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_8X
627 },
628 {{ 50001, 100000 },
629 HDMI_DEEP_COLOR_24BIT, 8, 10, 4, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_4X
630 },
631 {{ 100001, 200000 },
632 HDMI_DEEP_COLOR_24BIT, 4, 10, 2, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_2X
633 },
634 {{ 200001, 340000 },
635 HDMI_DEEP_COLOR_24BIT, 2, 10, 1, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_1X
636 },
637 {{ 340001, 600000 },
638 HDMI_DEEP_COLOR_24BIT, 1, 5, 1, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_40, INTERPOLATION_MODE_1X
639 },
640 {{ 25001, 50000 },
641 HDMI_DEEP_COLOR_30BIT, 16, 8, 8, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_8X
642 },
643 {{ 50001, 100000 },
644 HDMI_DEEP_COLOR_30BIT, 8, 8, 4, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_4X
645 },
646 {{ 100001, 200000 },
647 HDMI_DEEP_COLOR_30BIT, 4, 8, 2, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_2X
648 },
649 {{ 200001, 272000 },
650 HDMI_DEEP_COLOR_30BIT, 2, 8, 1, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_1X
651 },
652 {{ 272001, 340000 },
653 HDMI_DEEP_COLOR_30BIT, 2, 8, 1, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_40, INTERPOLATION_MODE_1X
654 },
655 {{ 340001, 600000 },
656 HDMI_DEEP_COLOR_30BIT, 1, 8, 1, PHY_LOOP_DIV_CFG_25, PHY_CLK_RATIO_1_40, INTERPOLATION_MODE_1X
657 },
658 {{ 25001, 50000 },
659 HDMI_DEEP_COLOR_36BIT, 16, 6, 8, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_8X
660 },
661 {{ 50001, 100000 },
662 HDMI_DEEP_COLOR_36BIT, 8, 6, 4, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_4X
663 },
664 {{ 100001, 200000 },
665 HDMI_DEEP_COLOR_36BIT, 4, 6, 2, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_2X
666 },
667 {{ 200001, 227000 },
668 HDMI_DEEP_COLOR_36BIT, 2, 6, 1, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_10, INTERPOLATION_MODE_1X
669 },
670 {{ 227001, 340000 },
671 HDMI_DEEP_COLOR_36BIT, 2, 6, 1, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_40, INTERPOLATION_MODE_1X
672 },
673 {{ 340001, 600000 },
674 HDMI_DEEP_COLOR_36BIT, 1, 3, 1, PHY_LOOP_DIV_CFG_22, PHY_CLK_RATIO_1_40, INTERPOLATION_MODE_1X
675 }
676 };
677
phy_rterm_mode_data_get(phy_rterm_mode r_term_mode)678 static phy_rterm_mode_data *phy_rterm_mode_data_get(phy_rterm_mode r_term_mode)
679 {
680 hi_u32 i;
681 phy_rterm_mode_data *phy_r_term_mode_cfg = HI_NULL;
682
683 for (i = 0, phy_r_term_mode_cfg = &g_phy_rterm_mode_deta[0];
684 (phy_r_term_mode_cfg && (i < hdmi_array_size(g_phy_rterm_mode_deta)));
685 phy_r_term_mode_cfg++, i++) {
686 if (phy_r_term_mode_cfg->r_term_mode == r_term_mode) {
687 return phy_r_term_mode_cfg;
688 }
689 }
690 hdmi_err("can't find param, r_term_mode:%u.\n", r_term_mode);
691
692 return &g_phy_rterm_mode_deta[0];
693 }
694
695 #ifndef PHY_SPEC_DEBUG
phy_transfer_cur2hex(hi_u32 cur)696 static hi_u32 phy_transfer_cur2hex(hi_u32 cur)
697 {
698 hi_u32 tmp;
699
700 if (cur < PHY_HWSPEC_I_16) {
701 tmp = cur;
702 } else if (cur < PHY_HWSPEC_I_28) {
703 tmp = (cur + 0x04);
704 } else if (cur < PHY_HWSPEC_I_32) {
705 tmp = (cur + 0x10);
706 } else if (cur <= PHY_HWSPEC_I_MAX) {
707 tmp = (cur + 0x14);
708 } else {
709 hdmi_err("%u is exceed max value %u.\n", cur, PHY_HWSPEC_I_MAX);
710 tmp = 0;
711 }
712
713 return tmp;
714 }
715
716 #ifdef PHY_CRAFT_S28
phy_hw_enhance_spec_set(const phy_hwspec_enhance_cfg * hw_spec_cfg)717 static hi_s32 phy_hw_enhance_spec_set(const phy_hwspec_enhance_cfg *hw_spec_cfg)
718 {
719 hi_u32 tmp;
720 errno_t ret;
721
722 hdmi_info("PHY HWSpec DeIMain clk:%u, d0:%u, d1:%u, d2:%u\n",
723 hw_spec_cfg->i_demain_clk, hw_spec_cfg->i_demain_d0, hw_spec_cfg->i_demain_d1, hw_spec_cfg->i_demain_d2);
724 hdmi_info("PHY HWSpec iMain clk:%u, d0:%u, d1:%u, d2:%u\n",
725 hw_spec_cfg->i_main_clk, hw_spec_cfg->i_main_d0, hw_spec_cfg->i_main_d1, hw_spec_cfg->i_main_d2);
726 hdmi_info("PHY HWSpec bFeedThruen clk:%u, d0:%u, d1:%u, d2:%u\n",
727 hw_spec_cfg->feedthru_cap_clk_en, hw_spec_cfg->feedthru_cap_d0_en,
728 hw_spec_cfg->feedthru_cap_d1_en, hw_spec_cfg->feedthru_cap_d2_en);
729 hdmi_info("PHY HWSpec enFeedThru clk:%u, d0:%u, d1:%u, d2:%u\n",
730 hw_spec_cfg->feedthru_cap_delay_clk, hw_spec_cfg->feedthru_cap_delay_d0,
731 hw_spec_cfg->feedthru_cap_delay_d1, hw_spec_cfg->feedthru_cap_delay_d2);
732 hdmi_info("PHY HWSpec RTermMode clk:%u, d0:%u, d1:%u, d2:%u\n",
733 hw_spec_cfg->rterm_mode_clk, hw_spec_cfg->rterm_mode_d0,
734 hw_spec_cfg->rterm_mode_d1, hw_spec_cfg->rterm_mode_d2);
735 hdmi_info("PHY HWSpec RTerm clk:0x%x, d0:0x%x, d1:0x%x, d2:0x%x\n",
736 hw_spec_cfg->rterm_clk, hw_spec_cfg->rterm_d0, hw_spec_cfg->rterm_d1, hw_spec_cfg->rterm_d2);
737
738 /* de iMain */
739 hdmi_reg_isel_main_de_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_demain_clk));
740 hdmi_reg_isel_main_de_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_demain_d0));
741 hdmi_reg_isel_main_de_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_demain_d1));
742 hdmi_reg_isel_main_de_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_demain_d2));
743 /* iMain */
744 hdmi_reg_isel_main_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_clk));
745 hdmi_reg_isel_main_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d0));
746 hdmi_reg_isel_main_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d1));
747 hdmi_reg_isel_main_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d2));
748 /* Feed-Through Cap Delay control */
749 tmp = hw_spec_cfg->feedthru_cap_delay_clk;
750 tmp = hw_spec_cfg->feedthru_cap_clk_en ? (tmp | PHY_FEEDTHRU_EN_MASK) : (tmp & (~PHY_FEEDTHRU_EN_MASK));
751 hdmi_reg_rsel_pre_clk_set(tmp);
752 tmp = hw_spec_cfg->feedthru_cap_delay_d0;
753 tmp = hw_spec_cfg->feedthru_cap_d0_en ? (tmp | PHY_FEEDTHRU_EN_MASK) : (tmp & (~PHY_FEEDTHRU_EN_MASK));
754 hdmi_reg_rsel_pre_d0_set(tmp);
755 tmp = hw_spec_cfg->feedthru_cap_delay_d1;
756 tmp = hw_spec_cfg->feedthru_cap_d1_en ? (tmp | PHY_FEEDTHRU_EN_MASK) : (tmp & (~PHY_FEEDTHRU_EN_MASK));
757 hdmi_reg_rsel_pre_d1_set(tmp);
758 tmp = hw_spec_cfg->feedthru_cap_delay_d2;
759 tmp = hw_spec_cfg->feedthru_cap_d2_en ? (tmp | PHY_FEEDTHRU_EN_MASK) : (tmp & (~PHY_FEEDTHRU_EN_MASK));
760 hdmi_reg_rsel_pre_d2_set(tmp);
761 /* R Term */
762 hdmi_reg_rt_clk_set(hw_spec_cfg->rterm_clk);
763 hdmi_reg_rt_d0_set(hw_spec_cfg->rterm_d0);
764 hdmi_reg_rt_d1_set(hw_spec_cfg->rterm_d1);
765 hdmi_reg_rt_d2_set(hw_spec_cfg->rterm_d2);
766 /* VCM sel */
767 hdmi_reg_test_set(hw_spec_cfg->vcm_sel);
768
769 /* status info set */
770 ret = memcpy_s(&g_hdmi_phy_info.spec_enhance_cfg, sizeof(g_hdmi_phy_info.spec_enhance_cfg),
771 hw_spec_cfg, sizeof(phy_hwspec_enhance_cfg));
772 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
773
774 return HI_SUCCESS;
775 }
776
trace_printf(hdmi_trace_len trace_len)777 static hi_void trace_printf(hdmi_trace_len trace_len)
778 {
779 switch (trace_len) {
780 case HDMI_TRACE_LEN_0:
781 hdmi_info("1.0 inch\n");
782 break;
783 case HDMI_TRACE_LEN_1:
784 hdmi_info("1.5 inch\n");
785 break;
786 case HDMI_TRACE_LEN_2:
787 hdmi_info("2.0 inch\n");
788 break;
789 case HDMI_TRACE_LEN_3:
790 hdmi_info("2.5 inch\n");
791 break;
792 case HDMI_TRACE_LEN_4:
793 hdmi_info("3.0 inch\n");
794 break;
795 case HDMI_TRACE_LEN_5:
796 hdmi_info("3.5 inch\n");
797 break;
798 case HDMI_TRACE_LEN_6:
799 hdmi_info("4.0 inch\n");
800 break;
801 case HDMI_TRACE_LEN_7:
802 hdmi_info("4.5 inch\n");
803 break;
804 case HDMI_TRACE_LEN_8:
805 hdmi_info("5.0 inch\n");
806 break;
807 default:
808 hdmi_info("default inch\n");
809 break;
810 }
811 }
812
phy_hw_enhance_spec_debug_data_get(phy_hwspec_enhance ** hwspec_enhance,hdmi_trace_len trace_len)813 static hi_u32 phy_hw_enhance_spec_debug_data_get(phy_hwspec_enhance **hwspec_enhance, hdmi_trace_len trace_len)
814 {
815 hi_u32 size;
816 phy_hwspec_enhance *hwspec = HI_NULL;
817
818 trace_printf(trace_len);
819
820 switch (trace_len) {
821 case HDMI_TRACE_LEN_0:
822 hwspec = &g_phy_hw_spec_enhance_1p0[0];
823 size = hdmi_array_size(g_phy_hw_spec_enhance_1p0);
824 break;
825 case HDMI_TRACE_LEN_1:
826 hwspec = &g_phy_hw_spec_enhance_1p5[0];
827 size = hdmi_array_size(g_phy_hw_spec_enhance_1p5);
828 break;
829 case HDMI_TRACE_LEN_2:
830 hwspec = &g_phy_hw_spec_enhance_2p0[0];
831 size = hdmi_array_size(g_phy_hw_spec_enhance_2p0);
832 break;
833 case HDMI_TRACE_LEN_3:
834 hwspec = &g_phy_hw_spec_enhance_2p5[0];
835 size = hdmi_array_size(g_phy_hw_spec_enhance_2p5);
836 break;
837 case HDMI_TRACE_LEN_4:
838 hwspec = &g_phy_hw_spec_enhance_3p0[0];
839 size = hdmi_array_size(g_phy_hw_spec_enhance_3p0);
840 break;
841 case HDMI_TRACE_LEN_5:
842 hwspec = &g_phy_hw_spec_enhance_3p5[0];
843 size = hdmi_array_size(g_phy_hw_spec_enhance_3p5);
844 break;
845 case HDMI_TRACE_LEN_6:
846 hwspec = &g_phy_hw_spec_enhance_4p0[0];
847 size = hdmi_array_size(g_phy_hw_spec_enhance_4p0);
848 break;
849 case HDMI_TRACE_LEN_7:
850 hwspec = &g_phy_hw_spec_enhance_4p5[0];
851 size = hdmi_array_size(g_phy_hw_spec_enhance_4p5);
852 break;
853 case HDMI_TRACE_LEN_8:
854 hwspec = &g_phy_hw_spec_enhance_5p0[0];
855 size = hdmi_array_size(g_phy_hw_spec_enhance_5p0);
856 break;
857 default:
858 hwspec = &g_phy_hw_spec_enhance[0];
859 size = hdmi_array_size(g_phy_hw_spec_enhance);
860 break;
861 }
862
863 *hwspec_enhance = hwspec;
864
865 return size;
866 }
867
phy_hw_enhance_spec_data_get(hi_u32 tmds_clk,hdmi_trace_len trace_len)868 static phy_hwspec_enhance_cfg *phy_hw_enhance_spec_data_get(hi_u32 tmds_clk, hdmi_trace_len trace_len)
869 {
870 hi_u32 i;
871 hi_u32 array_size;
872 phy_hwspec_enhance *phy_hw_enhance_spec = HI_NULL;
873 static hdmi_trace_len old_trace_len = HDMI_TRACE_BUTT;
874
875 /* default cfg */
876 if (trace_len == HDMI_TRACE_BUTT) {
877 phy_hw_enhance_spec = &g_phy_hw_spec_enhance[0];
878 array_size = hdmi_array_size(g_phy_hw_spec_enhance);
879 } else {
880 array_size = phy_hw_enhance_spec_debug_data_get(&phy_hw_enhance_spec, trace_len);
881 }
882
883 /* updata g_hdmi_phy_info just in change trace len. */
884 if ((phy_hw_enhance_spec != HI_NULL) && (trace_len != old_trace_len)) {
885 hdmi_info("trace change!(%u->%u), updata g_hdmi_phy_info\n", old_trace_len, trace_len);
886 old_trace_len = trace_len;
887 for (i = 0; i < HDMI_HW_PARAM_NUM; i++) {
888 g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_clk = phy_hw_enhance_spec[i].cfg.i_demain_clk;
889 g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data = phy_hw_enhance_spec[i].cfg.i_demain_d0;
890 g_hdmi_phy_info.hw_spec.hw_param[i].i_main_clk = phy_hw_enhance_spec[i].cfg.i_main_clk;
891 g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data = phy_hw_enhance_spec[i].cfg.i_main_d0;
892 g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_clk = phy_hw_enhance_spec[i].cfg.feedthru_cap_clk_en ?
893 (phy_hw_enhance_spec[i].cfg.feedthru_cap_delay_clk + 1) : 0;
894 g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data = phy_hw_enhance_spec[i].cfg.feedthru_cap_d0_en ?
895 (phy_hw_enhance_spec[i].cfg.feedthru_cap_delay_d0 + 1) : 0;
896
897 hdmi_info("stage[%u]: i_de_main_clk:%u i_de_main_data:%u\
898 i_main_clk:%u i_main_data:%u ft_cap_clk:%u ft_cap_data:%u\n", i,
899 g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_clk, g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data,
900 g_hdmi_phy_info.hw_spec.hw_param[i].i_main_clk, g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data,
901 g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_clk, g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data);
902 }
903 }
904
905 for (i = 0; ((phy_hw_enhance_spec != HI_NULL) && (i < array_size)); phy_hw_enhance_spec++, i++) {
906 if ((tmds_clk >= phy_hw_enhance_spec->range.clk_min) && (tmds_clk <= phy_hw_enhance_spec->range.clk_max)) {
907 return (&phy_hw_enhance_spec->cfg);
908 }
909 }
910
911 return HI_NULL;
912 }
913
phy_feedthru_en(phy_hwspec_enhance_cfg * phy_spec_cfg,const hdmi_hw_param * hw_param)914 static hi_void phy_feedthru_en(phy_hwspec_enhance_cfg *phy_spec_cfg, const hdmi_hw_param *hw_param)
915 {
916 if (hw_param->ft_cap_clk != 0) {
917 phy_spec_cfg->feedthru_cap_clk_en = HI_TRUE;
918 } else {
919 phy_spec_cfg->feedthru_cap_clk_en = HI_FALSE;
920 }
921
922 if (hw_param->ft_cap_data != 0) {
923 phy_spec_cfg->feedthru_cap_d0_en = HI_TRUE;
924 phy_spec_cfg->feedthru_cap_d1_en = HI_TRUE;
925 phy_spec_cfg->feedthru_cap_d2_en = HI_TRUE;
926 } else {
927 phy_spec_cfg->feedthru_cap_d0_en = HI_FALSE;
928 phy_spec_cfg->feedthru_cap_d1_en = HI_FALSE;
929 phy_spec_cfg->feedthru_cap_d2_en = HI_FALSE;
930 }
931
932 return;
933 }
934
phy_user_enhance_param_set(hi_u32 tmds_clk,phy_hwspec_enhance_cfg * phy_spec_cfg)935 static hi_void phy_user_enhance_param_set(hi_u32 tmds_clk, phy_hwspec_enhance_cfg *phy_spec_cfg)
936 {
937 hi_u8 i;
938 phy_hwspec_enhance *hw_spec = HI_NULL;
939
940 for (i = 0, hw_spec = &g_phy_hw_spec_enhance[0];
941 (hw_spec != HI_NULL && (i < hdmi_array_size(g_phy_hw_spec_enhance)));
942 hw_spec++, i++) {
943 if ((tmds_clk >= hw_spec->range.clk_min) && (tmds_clk <= hw_spec->range.clk_max)) {
944 phy_spec_cfg->i_demain_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_clk;
945 if (phy_spec_cfg->i_demain_d0 != g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data) {
946 phy_spec_cfg->i_demain_d0 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
947 phy_spec_cfg->i_demain_d1 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
948 phy_spec_cfg->i_demain_d2 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
949 }
950 phy_spec_cfg->i_main_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_clk;
951 if (phy_spec_cfg->i_main_d0 != g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data) {
952 phy_spec_cfg->i_main_d0 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
953 phy_spec_cfg->i_main_d1 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
954 phy_spec_cfg->i_main_d2 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
955 }
956 if (g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_clk > 0) {
957 phy_spec_cfg->feedthru_cap_delay_clk = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_clk - 1;
958 }
959 if ((g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data > 0) &&
960 (phy_spec_cfg->feedthru_cap_delay_d0 != (g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data - 1))) {
961 phy_spec_cfg->feedthru_cap_delay_d0 = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data - 1;
962 phy_spec_cfg->feedthru_cap_delay_d1 = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data - 1;
963 phy_spec_cfg->feedthru_cap_delay_d2 = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data - 1;
964 }
965 phy_feedthru_en(phy_spec_cfg, &g_hdmi_phy_info.hw_spec.hw_param[i]);
966
967 break;
968 }
969 }
970
971 return;
972 }
973
974 #else
975
phy_hw_spec_print(const phy_hw_spec_cfg * hw_spec_cfg)976 static hi_void phy_hw_spec_print(const phy_hw_spec_cfg *hw_spec_cfg)
977 {
978 hdmi_info("de_main clk:%u, d0:%u, d1:%u, d2:%u\n",
979 hw_spec_cfg->i_de_main_clk, hw_spec_cfg->i_de_main_d0, hw_spec_cfg->i_de_main_d1, hw_spec_cfg->i_de_main_d2);
980 hdmi_info("i_main clk:%u, d0:%u, d1:%u, d2:%u\n",
981 hw_spec_cfg->i_main_clk, hw_spec_cfg->i_main_d0, hw_spec_cfg->i_main_d1, hw_spec_cfg->i_main_d2);
982 hdmi_info("i_pre clk:%u, d0:%u, d1:%u, d2:%u\n",
983 hw_spec_cfg->i_pre_clk, hw_spec_cfg->i_pre_d0, hw_spec_cfg->i_pre_d1, hw_spec_cfg->i_pre_d2);
984 hdmi_info("r_pre clk:%u, d0:%u, d1:%u, d2:%u\n",
985 hw_spec_cfg->r_pre_clk, hw_spec_cfg->r_pre_d0, hw_spec_cfg->r_pre_d1, hw_spec_cfg->r_pre_d2);
986 hdmi_info("r_term clk:0x%x, d0:0x%x, d1:0x%x, d2:0x%x\n",
987 hw_spec_cfg->r_term_clk, hw_spec_cfg->r_term_d0, hw_spec_cfg->r_term_d1, hw_spec_cfg->r_term_d2);
988 }
989
phy_hw_spec_set(const phy_hw_spec_cfg * hw_spec_cfg)990 static hi_s32 phy_hw_spec_set(const phy_hw_spec_cfg *hw_spec_cfg)
991 {
992 hi_u32 tmp;
993 errno_t ret;
994
995 phy_hw_spec_print(hw_spec_cfg);
996
997 /* de i_main */
998 hdmi_reg_isel_main_de_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_main_clk));
999 hdmi_reg_isel_main_de_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_main_d0));
1000 hdmi_reg_isel_main_de_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_main_d1));
1001 hdmi_reg_isel_main_de_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_main_d2));
1002 /* i_main */
1003 hdmi_reg_isel_main_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_clk));
1004 hdmi_reg_isel_main_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d0));
1005 hdmi_reg_isel_main_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d1));
1006 hdmi_reg_isel_main_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_main_d2));
1007 /* de i_pre */
1008 hdmi_reg_isel_pre_de_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_pre_clk));
1009 hdmi_reg_isel_pre_de_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_pre_d0));
1010 hdmi_reg_isel_pre_de_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_pre_d1));
1011 hdmi_reg_isel_pre_de_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_de_pre_d2));
1012 /* i_pre */
1013 hdmi_reg_isel_pre_clk_set(phy_transfer_cur2hex(hw_spec_cfg->i_pre_clk));
1014 hdmi_reg_isel_pre_d0_set(phy_transfer_cur2hex(hw_spec_cfg->i_pre_d0));
1015 hdmi_reg_isel_pre_d1_set(phy_transfer_cur2hex(hw_spec_cfg->i_pre_d1));
1016 hdmi_reg_isel_pre_d2_set(phy_transfer_cur2hex(hw_spec_cfg->i_pre_d2));
1017 /* de R pre */
1018 hdmi_reg_rsel_pre_de_clk_set((hi_u32)(hw_spec_cfg->r_de_pre_clk));
1019 hdmi_reg_rsel_pre_de_d0_set((hi_u32)(hw_spec_cfg->r_de_pre_d0));
1020 hdmi_reg_rsel_pre_de_d1_set((hi_u32)(hw_spec_cfg->r_de_pre_d1));
1021 hdmi_reg_rsel_pre_de_d2_set((hi_u32)(hw_spec_cfg->r_de_pre_d2));
1022 /* R pre */
1023 hdmi_reg_rsel_pre_clk_set((hi_u32)(hw_spec_cfg->r_pre_clk));
1024 hdmi_reg_rsel_pre_d0_set((hi_u32)(hw_spec_cfg->r_pre_d0));
1025 hdmi_reg_rsel_pre_d1_set((hi_u32)(hw_spec_cfg->r_pre_d1));
1026 hdmi_reg_rsel_pre_d2_set((hi_u32)(hw_spec_cfg->r_pre_d2));
1027 /* R term */
1028 hdmi_reg_rt_clk_set(hw_spec_cfg->r_term_clk);
1029 hdmi_reg_rt_d0_set(hw_spec_cfg->r_term_d0);
1030 hdmi_reg_rt_d1_set(hw_spec_cfg->r_term_d1);
1031 hdmi_reg_rt_d2_set(hw_spec_cfg->r_term_d2);
1032 tmp = phy_rterm_mode_data_get(hw_spec_cfg->r_term_mode_clk)->mode_data_clk;
1033 tmp |= phy_rterm_mode_data_get(hw_spec_cfg->r_term_mode_d0)->mode_data_d0;
1034 tmp |= phy_rterm_mode_data_get(hw_spec_cfg->r_term_mode_d1)->mode_data_d1;
1035 tmp |= phy_rterm_mode_data_get(hw_spec_cfg->r_term_mode_d2)->mode_data_d2;
1036 hdmi_reg_gc_pd_rterm_set(tmp);
1037
1038 /* status info set */
1039 ret = memcpy_s(&g_hdmi_phy_info.hw_spec_cfg, sizeof(phy_hw_spec_cfg), hw_spec_cfg, sizeof(*hw_spec_cfg));
1040 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1041
1042 return HI_SUCCESS;
1043 }
1044
phy_hw_spec_data_get(hi_u32 tmds_clk,hdmi_trace_len trace_len)1045 static phy_hw_spec_cfg *phy_hw_spec_data_get(hi_u32 tmds_clk, hdmi_trace_len trace_len)
1046 {
1047 hi_u32 i;
1048 hi_u32 arrar_size;
1049 phy_hw_spec *spec = HI_NULL;
1050
1051 if (trace_len == HDMI_TRACE_LEN_0) {
1052 spec = &g_phy_hw_spec[0];
1053 arrar_size = hdmi_array_size(g_phy_hw_spec);
1054 } else if (trace_len == HDMI_TRACE_LEN_1) {
1055 spec = &g_phy_hw_spec1[0];
1056 arrar_size = hdmi_array_size(g_phy_hw_spec1);
1057 } else {
1058 spec = &g_phy_hw_spec2[0];
1059 arrar_size = hdmi_array_size(g_phy_hw_spec2);
1060 }
1061
1062 for (i = 0; (spec && (i < arrar_size)); spec++, i++) {
1063 if ((tmds_clk >= spec->phy_tmds_clk_range.clk_min) && (tmds_clk <= spec->phy_tmds_clk_range.clk_max)) {
1064 return (&spec->phy_spec_cfg);
1065 }
1066 }
1067
1068 return HI_NULL;
1069 }
1070
phy_user_param_set(hi_u32 tmds_clk,phy_hw_spec_cfg * phy_spec_cfg)1071 static hi_void phy_user_param_set(hi_u32 tmds_clk, phy_hw_spec_cfg *phy_spec_cfg)
1072 {
1073 hi_u8 i;
1074 phy_hw_spec *hw_spec = HI_NULL;
1075
1076 for (i = 0, hw_spec = &g_phy_hw_spec[0];
1077 (hw_spec != HI_NULL && (i < hdmi_array_size(g_phy_hw_spec)));
1078 hw_spec++, i++) {
1079 if ((tmds_clk >= hw_spec->phy_tmds_clk_range.clk_min) && (tmds_clk <= hw_spec->phy_tmds_clk_range.clk_max)) {
1080 if (phy_spec_cfg->i_de_main_d0 != g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data) {
1081 phy_spec_cfg->i_de_main_d0 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
1082 phy_spec_cfg->i_de_main_d1 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
1083 phy_spec_cfg->i_de_main_d2 = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
1084 }
1085 phy_spec_cfg->i_de_main_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_clk;
1086 if (phy_spec_cfg->i_main_d0 != g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data) {
1087 phy_spec_cfg->i_main_d0 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
1088 phy_spec_cfg->i_main_d1 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
1089 phy_spec_cfg->i_main_d2 = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
1090 }
1091 phy_spec_cfg->i_main_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_clk;
1092 break;
1093 }
1094 }
1095
1096 return;
1097 }
1098 #endif
1099
1100 #else
hal_hdmi_phy_spec_regs_set(const hdmi_phy_hw_spec_cfg * hdmi_spec_cfg)1101 static hi_void hal_hdmi_phy_spec_regs_set(const hdmi_phy_hw_spec_cfg *hdmi_spec_cfg)
1102 {
1103 hi_u32 tmp;
1104
1105 if ((hdmi_spec_cfg->tmds_clk >= TMDS_CLOCK_25M) && (hdmi_spec_cfg->tmds_clk <= TMDS_CLOCK_100M)) {
1106 hdmi_reg_write_u32(0x11400068, 0x00861865);
1107 hdmi_reg_write_u32(0x1140006c, 0x18180000);
1108 hdmi_reg_write_u32(0x11400070, 0x00000618);
1109 hdmi_reg_write_u32(0x11400074, 0x0001B6C0);
1110 hdmi_reg_write_u32(0x11400078, 0x20202000);
1111 tmp = hdmi_reg_read_u32(0x11400064);
1112 tmp |= 0xfd << 11; /* 11'b, BIT[19:12] */
1113 hdmi_reg_write_u32(0x11400064, tmp);
1114 } else if ((hdmi_spec_cfg->tmds_clk > TMDS_CLOCK_100M) && (hdmi_spec_cfg->tmds_clk <= TMDS_CLOCK_165M)) {
1115 hdmi_reg_write_u32(0x11400068, 0x00C71C65);
1116 hdmi_reg_write_u32(0x1140006c, 0x18600000);
1117 hdmi_reg_write_u32(0x11400070, 0x00000618);
1118 hdmi_reg_write_u32(0x11400074, 0x0001B780);
1119 hdmi_reg_write_u32(0x11400078, 0x20202000);
1120 tmp = hdmi_reg_read_u32(0x11400064);
1121 tmp |= 0xfd << 11; /* 11'b, BIT[19:12] */
1122 hdmi_reg_write_u32(0x11400064, tmp);
1123 } else if ((hdmi_spec_cfg->tmds_clk > TMDS_CLOCK_165M) && (hdmi_spec_cfg->tmds_clk <= TMDS_CLOCK_340M)) {
1124 hdmi_reg_write_u32(0x11400068, 0x00C71C65);
1125 hdmi_reg_write_u32(0x1140006c, 0x18600000);
1126 hdmi_reg_write_u32(0x11400070, 0x00000618);
1127 hdmi_reg_write_u32(0x11400074, 0x0001B6C0);
1128 hdmi_reg_write_u32(0x11400078, 0x60606000);
1129 tmp = hdmi_reg_read_u32(0x11400064);
1130 tmp |= 0x55 << 11; /* 11'b, BIT[19:12] */
1131 hdmi_reg_write_u32(0x11400064, tmp);
1132 }
1133
1134 return;
1135 }
1136 #endif
1137
phy_ssc_data_get(hi_u32 tmds_clk)1138 static phy_ssc_cfg *phy_ssc_data_get(hi_u32 tmds_clk)
1139 {
1140 hi_u32 i;
1141 phy_ssc *ssc_cfg = HI_NULL;
1142
1143 for (i = 0, ssc_cfg = &g_phy_ssc_cfg[0]; (ssc_cfg && (i < hdmi_array_size(g_phy_ssc_cfg))); ssc_cfg++, i++) {
1144 if ((tmds_clk >= ssc_cfg->phy_tmds_clk_range.clk_min) && (tmds_clk <= ssc_cfg->phy_tmds_clk_range.clk_max)) {
1145 return (&ssc_cfg->ssc_cfg);
1146 }
1147 }
1148
1149 return HI_NULL;
1150 }
1151
phy_div_mode_set(phy_div_mode div_mode)1152 static hi_void phy_div_mode_set(phy_div_mode div_mode)
1153 {
1154 hdmi_reg_divsel_set(div_mode);
1155 return;
1156 }
1157
phy_loop_div_set(hi_u32 loop_div)1158 static hi_void phy_loop_div_set(hi_u32 loop_div)
1159 {
1160 hdmi_reg_fb_set(loop_div);
1161 return;
1162 }
1163
phy_clk_ratio_set(phy_clk_ratio clk_ratio)1164 static hi_void phy_clk_ratio_set(phy_clk_ratio clk_ratio)
1165 {
1166 hi_u32 phy_fifo_ck_l = 0; // 30bit
1167 hi_u32 phy_fifo_ck_h = 0; // 10bit
1168
1169 switch (clk_ratio) {
1170 case PHY_CLK_RATIO_1_10:
1171 phy_fifo_ck_l = PHY_RATIO_1_10_MASK;
1172 phy_fifo_ck_l <<= 10; /* 10'b, BIT[15:11] */
1173 phy_fifo_ck_l |= PHY_RATIO_1_10_MASK;
1174 phy_fifo_ck_l <<= 10; /* 10'b, BIT[25:11] */
1175 phy_fifo_ck_l |= PHY_RATIO_1_10_MASK;
1176 phy_fifo_ck_h = PHY_RATIO_1_10_MASK;
1177 break;
1178 case PHY_CLK_RATIO_1_40:
1179 phy_fifo_ck_l = PHY_RATIO_1_40_MASK;
1180 phy_fifo_ck_h = 0;
1181 break;
1182 default:
1183 hdmi_err("clk_ratio %u is invalid\n", clk_ratio);
1184 return;
1185 }
1186 hdmi_reg_aphy_data_clk_height_set(phy_fifo_ck_h);
1187 hdmi_reg_aphy_data_clk_low_set(phy_fifo_ck_l);
1188
1189 return;
1190 }
1191
phy_transfer_hex2cur(hi_u32 reg_hex)1192 static hi_u32 phy_transfer_hex2cur(hi_u32 reg_hex)
1193 {
1194 hi_u32 cur;
1195
1196 if (reg_hex < 0x10) {
1197 cur = reg_hex;
1198 } else if ((reg_hex >= 0x10) && (reg_hex < 0x20)) {
1199 cur = (reg_hex - 0x04);
1200 } else if ((reg_hex >= 0x20) && (reg_hex < 0x30)) {
1201 cur = (reg_hex - 0x10);
1202 } else if ((reg_hex >= 0x30) && (reg_hex < 0x40)) {
1203 cur = (reg_hex - 0x14);
1204 } else {
1205 hdmi_err("get current(%u) error.\n", reg_hex);
1206 cur = reg_hex;
1207 }
1208
1209 return cur;
1210 }
1211
phy_cur_hw_param_get(hdmi_hw_param * hw_param)1212 static hi_void phy_cur_hw_param_get(hdmi_hw_param *hw_param)
1213 {
1214 hi_u32 tmp;
1215
1216 tmp = hdmi_reg_isel_main_de_clk_get();
1217 hw_param->i_de_main_clk = phy_transfer_hex2cur(tmp);
1218 tmp = hdmi_reg_isel_main_de_d0_get();
1219 hw_param->i_de_main_data = phy_transfer_hex2cur(tmp);
1220 tmp = hdmi_reg_isel_main_clk_get();
1221 hw_param->i_main_clk = phy_transfer_hex2cur(tmp);
1222 tmp = hdmi_reg_isel_main_d0_get();
1223 hw_param->i_main_data = phy_transfer_hex2cur(tmp);
1224
1225 tmp = hdmi_reg_rsel_pre_clk_get();
1226 /* if enable */
1227 if (tmp & PHY_FEEDTHRU_EN_MASK) {
1228 tmp &= PHY_FEEDTHRU_DATA_MASK; /* get data */
1229 tmp++; /* reg val add 1 */
1230 hw_param->ft_cap_clk = phy_transfer_hex2cur(tmp);
1231 } else {
1232 hw_param->ft_cap_clk = 0;
1233 }
1234
1235 tmp = hdmi_reg_rsel_pre_d0_get();
1236 /* if enable */
1237 if (tmp & PHY_FEEDTHRU_EN_MASK) {
1238 tmp &= PHY_FEEDTHRU_DATA_MASK; /* get data */
1239 tmp++; /* reg val add 1 */
1240 hw_param->ft_cap_data = phy_transfer_hex2cur(tmp);
1241 } else {
1242 hw_param->ft_cap_data = 0;
1243 }
1244
1245 return;
1246 }
1247
phy_default_spec_set(hi_void)1248 static hi_void phy_default_spec_set(hi_void)
1249 {
1250 hi_u8 i;
1251 hdmi_hw_spec *spec = HI_NULL;
1252
1253 spec = &g_hdmi_phy_info.hw_spec;
1254 for (i = 0; i < HDMI_HW_PARAM_NUM; i++) {
1255 #ifdef PHY_CRAFT_S28
1256 spec->hw_param[i].i_de_main_clk = g_phy_hw_spec_enhance[i].cfg.i_demain_clk;
1257 spec->hw_param[i].i_de_main_data = g_phy_hw_spec_enhance[i].cfg.i_demain_d0;
1258 spec->hw_param[i].i_main_clk = g_phy_hw_spec_enhance[i].cfg.i_main_clk;
1259 spec->hw_param[i].i_main_data = g_phy_hw_spec_enhance[i].cfg.i_main_d0;
1260 spec->hw_param[i].ft_cap_clk = g_phy_hw_spec_enhance[i].cfg.feedthru_cap_clk_en ?
1261 (g_phy_hw_spec_enhance[i].cfg.feedthru_cap_delay_clk + 1) : 0;
1262 spec->hw_param[i].ft_cap_data = g_phy_hw_spec_enhance[i].cfg.feedthru_cap_d0_en ?
1263 (g_phy_hw_spec_enhance[i].cfg.feedthru_cap_delay_d0 + 1) : 0;
1264 #else
1265 spec->hw_param[i].i_de_main_clk = g_phy_hw_spec[i].phy_spec_cfg.i_de_main_clk;
1266 spec->hw_param[i].i_de_main_data = g_phy_hw_spec[i].phy_spec_cfg.i_de_main_d0;
1267 spec->hw_param[i].i_main_clk = g_phy_hw_spec[i].phy_spec_cfg.i_main_clk;
1268 spec->hw_param[i].i_main_data = g_phy_hw_spec[i].phy_spec_cfg.i_main_d0;
1269 #endif
1270 }
1271
1272 return;
1273 }
1274
hal_hdmi_phy_ssc_on(hi_u32 span_fb,hi_u32 step_fb)1275 static hi_void hal_hdmi_phy_ssc_on(hi_u32 span_fb, hi_u32 step_fb)
1276 {
1277 /* step 1 */
1278 hdmi_reg_step_fb_set(step_fb);
1279 hdmi_reg_span_fb_set(span_fb);
1280 /* step 2 */
1281 hdmi_reg_ssc_mode_fb_set(HI_TRUE);
1282 /* step 3 */
1283 hdmi_reg_load_fb_set(HI_FALSE);
1284 hdmi_reg_load_fb_set(HI_TRUE);
1285 hdmi_reg_load_fb_set(HI_FALSE);
1286 /* step 4 */
1287 hdmi_reg_gc_txpll_test_set(PHY_TXPLL_TEST_ON);
1288 /* step 5 */
1289 hdmi_reg_gc_txpll_en_sscdiv_set(HI_TRUE);
1290
1291 return;
1292 }
1293
hal_hdmi_phy_ssc_off(hdmi_deep_color deep_color)1294 static hi_void hal_hdmi_phy_ssc_off(hdmi_deep_color deep_color)
1295 {
1296 hdmi_reg_step_fb_set(0);
1297 hdmi_reg_span_fb_set(0);
1298 /* 12bit need to enter decimal mode */
1299 if (deep_color == HDMI_DEEP_COLOR_36BIT) {
1300 /* step 1 */
1301 hdmi_reg_ssc_mode_fb_set(HI_TRUE);
1302 /* step 2 */
1303 hdmi_reg_load_fb_set(HI_FALSE);
1304 hdmi_reg_load_fb_set(HI_TRUE);
1305 hdmi_reg_load_fb_set(HI_FALSE);
1306 /* step 3 */
1307 hdmi_reg_gc_txpll_test_set(PHY_TXPLL_TEST_ON);
1308 /* step 4 */
1309 hdmi_reg_gc_txpll_en_sscdiv_set(HI_TRUE);
1310 } else {
1311 hdmi_reg_gc_txpll_en_sscdiv_set(HI_FALSE);
1312 hdmi_reg_gc_txpll_test_set(PHY_TXPLL_TEST_OFF);
1313 hdmi_reg_ssc_mode_fb_set(HI_FALSE);
1314 }
1315
1316 return;
1317 }
1318
phy_div_cfg_get(hi_u32 pix_clk,hdmi_deep_color deep_clr)1319 static phy_div_cfg *phy_div_cfg_get(hi_u32 pix_clk, hdmi_deep_color deep_clr)
1320 {
1321 hi_u32 i;
1322 phy_div_cfg *div_cfg = HI_NULL;
1323
1324 for (i = 0, div_cfg = &g_phy_div_cfg[0]; (div_cfg && (i < hdmi_array_size(g_phy_div_cfg))); div_cfg++, i++) {
1325 if ((pix_clk >= div_cfg->pix_clk_range.clk_min) &&
1326 (pix_clk <= div_cfg->pix_clk_range.clk_max) &&
1327 (deep_clr == div_cfg->deep_color)) {
1328 return div_cfg;
1329 }
1330 }
1331 hdmi_err("can't find param, tmds_clk:%u, deep_clr=%u.\n", pix_clk, deep_clr);
1332
1333 return &g_phy_div_cfg[1];
1334 }
1335
phy_rterm_init(hi_void)1336 static hi_void phy_rterm_init(hi_void)
1337 {
1338 hi_u32 i;
1339 hi_u32 tmp_regval;
1340 phy_rterm_mode_data rterm_mode = {0};
1341 phy_rterm_mode mode_clk = PHY_RTERM_MODE_SINGLE;
1342 phy_rterm_mode mode_d0 = PHY_RTERM_MODE_SINGLE;
1343 phy_rterm_mode mode_d1 = PHY_RTERM_MODE_SINGLE;
1344 phy_rterm_mode mode_d2 = PHY_RTERM_MODE_SINGLE;
1345
1346 tmp_regval = hdmi_reg_gc_pd_rterm_get();
1347 rterm_mode.mode_data_clk = tmp_regval & 0x03;
1348 rterm_mode.mode_data_d0 = tmp_regval & 0x0C;
1349 rterm_mode.mode_data_d1 = tmp_regval & 0x30;
1350 rterm_mode.mode_data_d2 = tmp_regval & 0xC0;
1351
1352 for (i = 0; i < hdmi_array_size(g_phy_rterm_mode_deta); i++) {
1353 if (rterm_mode.mode_data_clk == g_phy_rterm_mode_deta[i].mode_data_clk) {
1354 mode_clk = g_phy_rterm_mode_deta[i].r_term_mode;
1355 }
1356 if (rterm_mode.mode_data_d0 == g_phy_rterm_mode_deta[i].mode_data_d0) {
1357 mode_d0 = g_phy_rterm_mode_deta[i].r_term_mode;
1358 }
1359 if (rterm_mode.mode_data_d1 == g_phy_rterm_mode_deta[i].mode_data_d1) {
1360 mode_d1 = g_phy_rterm_mode_deta[i].r_term_mode;
1361 }
1362 if (rterm_mode.mode_data_d2 == g_phy_rterm_mode_deta[i].mode_data_d2) {
1363 mode_d2 = g_phy_rterm_mode_deta[i].r_term_mode;
1364 }
1365 }
1366
1367 #ifdef PHY_CRAFT_S28
1368 g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_clk = mode_clk;
1369 g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d0 = mode_d0;
1370 g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d1 = mode_d1;
1371 g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d2 = mode_d2;
1372 #endif
1373
1374 hdmi_info("clk:%d, d0:%d, d1:%d, d2:%d, RTerm:0x%x\n",
1375 mode_clk, mode_d0, mode_d1, mode_d2, tmp_regval);
1376
1377 return;
1378 }
1379
1380 /* hisense LED32H130, this TV can't resume when RTerm is opend */
phy_rterm_set(hi_bool enable)1381 static hi_void phy_rterm_set(hi_bool enable)
1382 {
1383 #ifdef PHY_CRAFT_S28
1384 hi_u32 tmp;
1385
1386 if (enable == HI_TRUE) {
1387 tmp = phy_rterm_mode_data_get(g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_clk)->mode_data_clk;
1388 tmp |= phy_rterm_mode_data_get(g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d0)->mode_data_d0;
1389 tmp |= phy_rterm_mode_data_get(g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d1)->mode_data_d1;
1390 tmp |= phy_rterm_mode_data_get(g_hdmi_phy_info.spec_enhance_cfg.rterm_mode_d2)->mode_data_d2;
1391 } else {
1392 tmp = 0x1FF;
1393 }
1394 hdmi_info("RTerm:0x%x\n", tmp);
1395 hdmi_reg_gc_pd_rterm_set(tmp);
1396
1397 #else
1398 hi_unused(enable);
1399 #endif
1400
1401 return;
1402 }
1403
1404
hal_hdmi_phy_init(const hdmi_hal_init * hal_init)1405 hi_s32 hal_hdmi_phy_init(const hdmi_hal_init *hal_init)
1406 {
1407 hdmi_if_fpga_return(HI_SUCCESS);
1408 hdmi_if_null_return(hal_init, HI_FAILURE);
1409
1410 if (!g_hdmi_phy_info.init) {
1411 if (hal_init->phy_addr == HI_NULL && hal_init->base_addr != HI_NULL) {
1412 hdmi_reg_tx_phy_init((hal_init->base_addr + HDMI_TX_BASE_ADDR_DPHY));
1413 } else if (hal_init->phy_addr != HI_NULL) {
1414 hdmi_reg_tx_phy_init(hal_init->phy_addr);
1415 } else {
1416 hdmi_err("null pointer!\n");
1417 return HI_FAILURE;
1418 }
1419
1420 /* init */
1421 hdmi_reg_txpll_icp_ictrl_set(PHY_I_CHARGE_PUMP);
1422 hdmi_reg_txpll_divsel_loop_set(PHY_PLL_LOOP_DEVIDER);
1423 hdmi_reg_sscin_bypass_en_set(HI_TRUE);
1424 hdmi_reg_pllfbmash111_en_set(HI_TRUE);
1425 phy_default_spec_set();
1426 phy_rterm_init();
1427 g_hdmi_phy_info.init = HI_TRUE;
1428 }
1429
1430 return HI_SUCCESS;
1431 }
1432
hal_hdmi_phy_deinit(hi_void)1433 hi_s32 hal_hdmi_phy_deinit(hi_void)
1434 {
1435 hdmi_if_fpga_return(HI_SUCCESS);
1436 hdmi_if_false_return(g_hdmi_phy_info.init, HI_FAILURE);
1437
1438 hal_hdmi_phy_reset();
1439 hdmi_reg_tx_phy_deinit();
1440 g_hdmi_phy_info.init = HI_FALSE;
1441
1442 return HI_SUCCESS;
1443 }
1444
hal_hdmi_phy_reset(hi_void)1445 hi_void hal_hdmi_phy_reset(hi_void)
1446 {
1447 hdmi_if_fpga_return_void();
1448 hdmi_if_false_return_void(g_hdmi_phy_info.init);
1449
1450 hal_hdmi_phy_oe_set(HI_FALSE);
1451 hal_hdmi_phy_power_set(HI_FALSE);
1452 drv_hdmi_prod_crg_phy_reset_set(HI_TRUE);
1453
1454 return;
1455 }
1456
hal_hdmi_phy_power_get(hi_bool * enable)1457 hi_s32 hal_hdmi_phy_power_get(hi_bool *enable)
1458 {
1459 phy_power_cfg power_cfg = {0};
1460
1461 hdmi_if_fpga_return(HI_SUCCESS);
1462 hdmi_if_false_return(g_hdmi_phy_info.init, HI_FAILURE);
1463 hdmi_if_null_return(enable, HI_FAILURE);
1464
1465 power_cfg.phy_gc_txpll_pd = hdmi_reg_gc_txpll_pd_get();
1466 power_cfg.phy_gc_rxsense_pd = hdmi_reg_gc_pd_rxsense_get();
1467 power_cfg.phy_gc_ldo_pd = hdmi_reg_gc_pd_ldo_get();
1468 power_cfg.phy_gc_de_pd = hdmi_reg_gc_pd_de_get();
1469 power_cfg.phy_gc_bist_pd = hdmi_reg_gc_pd_bist_get();
1470
1471 if ((power_cfg.phy_gc_txpll_pd == PHY_POWER_ON) && (power_cfg.phy_gc_rxsense_pd == PHY_POWER_ON) &&
1472 (power_cfg.phy_gc_ldo_pd == PHY_POWER_ON) && power_cfg.phy_gc_bist_pd) {
1473 *enable = HI_TRUE;
1474 } else if (power_cfg.phy_gc_txpll_pd && power_cfg.phy_gc_rxsense_pd &&
1475 (PHY_POWER_LDO_OFF & power_cfg.phy_gc_ldo_pd) && (PHY_POWER_OFF & (hi_u32)power_cfg.phy_gc_bist_pd)) {
1476 *enable = HI_FALSE;
1477 } else {
1478 hdmi_warn("phy power configure is abnormal\n");
1479 *enable = HI_FALSE;
1480 }
1481
1482 return HI_SUCCESS;
1483 }
1484
hal_hdmi_phy_power_set(hi_bool enable)1485 hi_void hal_hdmi_phy_power_set(hi_bool enable)
1486 {
1487 hdmi_if_fpga_return_void();
1488 hdmi_if_false_return_void(g_hdmi_phy_info.init);
1489
1490 if (enable) {
1491 hdmi_reg_gc_txpll_pd_set(PHY_POWER_ON);
1492 hdmi_reg_gc_pd_rxsense_set(PHY_POWER_ON);
1493 hdmi_reg_gc_pd_ldo_set(PHY_POWER_ON);
1494 } else {
1495 hdmi_reg_gc_txpll_pd_set(PHY_POWER_OFF);
1496 hdmi_reg_gc_pd_rxsense_set(PHY_POWER_OFF);
1497 hdmi_reg_gc_pd_ldo_set(PHY_POWER_OFF);
1498 }
1499 hdmi_reg_gc_pd_bist_set(PHY_POWER_OFF);
1500 g_hdmi_phy_info.power_enable = enable;
1501
1502 return;
1503 }
1504
hal_hdmi_phy_oe_set(hi_bool enable)1505 hi_void hal_hdmi_phy_oe_set(hi_bool enable)
1506 {
1507 hi_u32 oe;
1508 hi_u32 de_main_power = PHY_POWER_OFF;
1509
1510 hdmi_if_fpga_return_void();
1511 hdmi_if_false_return_void(g_hdmi_phy_info.init);
1512 oe = enable ? PHY_OE_ON : PHY_OE_OFF;
1513 /* de-emphasis must be power down. */
1514 if (enable) {
1515 if (hdmi_reg_isel_main_de_clk_get() != 0) {
1516 de_main_power &= PHY_POWER_ON_MASK_CLK;
1517 }
1518 if (hdmi_reg_isel_main_de_d0_get() != 0) {
1519 de_main_power &= PHY_POWER_ON_MASK_D0;
1520 }
1521 if (hdmi_reg_isel_main_de_d1_get() != 0) {
1522 de_main_power &= PHY_POWER_ON_MASK_D1;
1523 }
1524 if (hdmi_reg_isel_main_de_d2_get() != 0) {
1525 de_main_power &= PHY_POWER_ON_MASK_D2;
1526 }
1527 }
1528 hdmi_reg_gc_pd_de_set(de_main_power);
1529 phy_rterm_set(enable);
1530 hdmi_reg_gc_pd_set(oe);
1531 g_hdmi_phy_info.oe_enable = enable;
1532
1533 return;
1534 }
1535
hal_hdmi_phy_oe_get(hi_bool * enable)1536 hi_s32 hal_hdmi_phy_oe_get(hi_bool *enable)
1537 {
1538 hi_bool phy_reset = HI_FALSE;
1539
1540 hdmi_if_fpga_return(HI_SUCCESS);
1541 hdmi_if_false_return(g_hdmi_phy_info.init, HI_FAILURE);
1542 hdmi_if_null_return(enable, HI_FAILURE);
1543
1544 drv_hdmi_prod_crg_phy_reset_get(&phy_reset);
1545 if (!phy_reset) {
1546 *enable = (hdmi_reg_gc_pd_get() == PHY_OE_ON) ? HI_TRUE : HI_FALSE;
1547 } else {
1548 *enable = HI_FALSE;
1549 }
1550
1551 return HI_SUCCESS;
1552 }
1553
1554 /* for video path */
hal_hdmi_phy_tmds_set(hdmi_phy_tmds_cfg * hdmi_tmds_cfg)1555 hi_s32 hal_hdmi_phy_tmds_set(hdmi_phy_tmds_cfg *hdmi_tmds_cfg)
1556 {
1557 errno_t ret;
1558 phy_div_cfg *div_cfg = HI_NULL;
1559 hdmi_deep_color dp_color;
1560 hdmi_crg_cfg crg_cfg = {0};
1561 hdmi_phy_ssc_cfg hdmi_ssc_cfg = {0};
1562 hdmi_phy_hw_spec_cfg hdmi_hw_spec_cfg = {0};
1563
1564 hdmi_if_fpga_return(HI_SUCCESS);
1565 hdmi_if_false_return(g_hdmi_phy_info.init, HI_FAILURE);
1566 hdmi_if_null_return(hdmi_tmds_cfg, HI_FAILURE);
1567
1568 dp_color = hdmi_tmds_cfg->deep_color;
1569 if (dp_color == HDMI_DEEP_COLOR_OFF) {
1570 dp_color = HDMI_DEEP_COLOR_24BIT;
1571 }
1572
1573 /* get config para */
1574 div_cfg = phy_div_cfg_get(hdmi_tmds_cfg->pixel_clk, dp_color);
1575 hdmi_if_null_return(div_cfg, HI_FAILURE);
1576
1577 hal_hdmi_phy_power_set(HI_TRUE);
1578 /* set phy div mode */
1579 phy_div_mode_set(div_cfg->div_mode);
1580 /* set crg div */
1581 crg_cfg.ssc_bypass_div = div_cfg->ssc_byp_div;
1582 crg_cfg.tmds_clk_div = div_cfg->tmds_nxdiv;
1583 drv_hdmi_prod_crg_div_set(&crg_cfg);
1584 /* must delay 500us after CRG register config finished. */
1585 osal_msleep(1);
1586 /* set clk ratio */
1587 phy_clk_ratio_set(div_cfg->clk_ratio);
1588 /* set loopdiv */
1589 phy_loop_div_set(div_cfg->loop_div);
1590 /* spread spectrum ctrl(ssc) */
1591 hdmi_ssc_cfg.pix_clk = hdmi_tmds_cfg->pixel_clk;
1592 hdmi_ssc_cfg.tmds_clk = hdmi_tmds_cfg->tmds_clk;
1593 hdmi_ssc_cfg.deep_color = dp_color;
1594 hdmi_ssc_cfg.phy_ssc.ssc_enable = hdmi_tmds_cfg->emi_enable;
1595 hdmi_ssc_cfg.phy_ssc.ssc_debug_en = HI_FALSE;
1596 hal_hdmi_phy_ssc_set(&hdmi_ssc_cfg);
1597
1598 /* set hard_ware specification */
1599 hdmi_hw_spec_cfg.tmds_clk = hdmi_tmds_cfg->tmds_clk;
1600 hdmi_hw_spec_cfg.trace_len = hdmi_tmds_cfg->trace_len;
1601 hdmi_hw_spec_cfg.hdmi_phy_spec.hw_spec_debug_en = HI_FALSE;
1602 hal_hdmi_phy_spec_set(&hdmi_hw_spec_cfg);
1603 /* status info set */
1604 ret = memcpy_s(&g_hdmi_phy_info.tmds_cfg, sizeof(hdmi_phy_tmds_cfg), hdmi_tmds_cfg, sizeof(hdmi_phy_tmds_cfg));
1605 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1606
1607 return HI_SUCCESS;
1608 }
1609
1610 /* spread spectrum ctrl(ssc) */
hdmi_phy_spec_set(hdmi_phy_hw_spec_cfg * hdmi_spec_cfg)1611 static hi_s32 hdmi_phy_spec_set(hdmi_phy_hw_spec_cfg *hdmi_spec_cfg)
1612 {
1613 errno_t ret;
1614
1615 #ifdef PHY_CRAFT_S28
1616 phy_hwspec_enhance_cfg enhance_spec = {0};
1617 phy_hwspec_enhance_cfg *phy_hw_enhance_spec = HI_NULL;
1618
1619 phy_hw_enhance_spec =
1620 hdmi_spec_cfg->hdmi_phy_spec.hw_spec_debug_en ? &hdmi_spec_cfg->hdmi_phy_spec.enhance_cfg :
1621 phy_hw_enhance_spec_data_get(hdmi_spec_cfg->tmds_clk, hdmi_spec_cfg->trace_len);
1622 hdmi_if_null_return(phy_hw_enhance_spec, HI_FAILURE);
1623 ret = memcpy_s(&enhance_spec, sizeof(phy_hwspec_enhance_cfg), phy_hw_enhance_spec, sizeof(*phy_hw_enhance_spec));
1624 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1625 phy_user_enhance_param_set(hdmi_spec_cfg->tmds_clk, &enhance_spec);
1626 ret = phy_hw_enhance_spec_set(&enhance_spec);
1627 #else
1628 phy_hw_spec_cfg spec_cfg = {0};
1629 phy_hw_spec_cfg *phy_hw_spec_cfg_tmp = HI_NULL;
1630
1631 phy_hw_spec_cfg_tmp =
1632 hdmi_spec_cfg->hdmi_phy_spec.hw_spec_debug_en ? &hdmi_spec_cfg->hdmi_phy_spec.spec_cfg :
1633 phy_hw_spec_data_get(hdmi_spec_cfg->tmds_clk, hdmi_spec_cfg->trace_len);
1634 hdmi_if_null_return(phy_hw_spec_cfg_tmp, HI_FAILURE);
1635 ret = memcpy_s(&spec_cfg, sizeof(phy_hw_spec_cfg), phy_hw_spec_cfg_tmp, sizeof(*phy_hw_spec_cfg_tmp));
1636 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1637 phy_user_param_set(hdmi_spec_cfg->tmds_clk, &spec_cfg);
1638
1639 ret = phy_hw_spec_set(&spec_cfg);
1640 #endif
1641
1642 return ret;
1643 }
1644
1645 /* for video path & debug */
hal_hdmi_phy_spec_set(hdmi_phy_hw_spec_cfg * hdmi_spec_cfg)1646 hi_s32 hal_hdmi_phy_spec_set(hdmi_phy_hw_spec_cfg *hdmi_spec_cfg)
1647 {
1648 hi_s32 ret = HI_SUCCESS;
1649
1650 hdmi_if_fpga_return(HI_SUCCESS);
1651 hdmi_if_null_return(hdmi_spec_cfg, HI_FAILURE);
1652
1653 #ifndef PHY_SPEC_DEBUG
1654 ret = hdmi_phy_spec_set(hdmi_spec_cfg);
1655 #else
1656 hdmi_if_false_return(g_hdmi_phy_info.init, HI_FAILURE);
1657 hdmi_if_null_return(hdmi_spec_cfg, HI_FAILURE);
1658 hal_hdmi_phy_spec_regs_set(hdmi_spec_cfg);
1659 #endif
1660
1661 return ret;
1662 }
1663
1664 /* for video path & debug */
hal_hdmi_phy_ssc_set(hdmi_phy_ssc_cfg * hdmi_ssc_cfg)1665 hi_void hal_hdmi_phy_ssc_set(hdmi_phy_ssc_cfg *hdmi_ssc_cfg)
1666 {
1667 errno_t ret;
1668 hi_u32 phy_ref_clk = 0;
1669 hi_u32 span_fb, step_fb, tmp;
1670 hdmi_deep_color dp_color;
1671 phy_ssc_cfg *phy_ssc_cfg_tmp = HI_NULL;
1672 phy_div_cfg *div_cfg = HI_NULL;
1673
1674 hdmi_if_fpga_return_void();
1675 hdmi_if_false_return_void(g_hdmi_phy_info.init);
1676 hdmi_if_null_return_void(hdmi_ssc_cfg);
1677
1678 dp_color = hdmi_ssc_cfg->deep_color;
1679 if (dp_color == HDMI_DEEP_COLOR_OFF) {
1680 dp_color = HDMI_DEEP_COLOR_24BIT;
1681 }
1682
1683 /* get config para */
1684 div_cfg = phy_div_cfg_get(hdmi_ssc_cfg->pix_clk, dp_color);
1685 hdmi_if_null_return_void(div_cfg);
1686
1687 /* spread spectrum ctrl(ssc) */
1688 if (hdmi_ssc_cfg->phy_ssc.ssc_enable) {
1689 phy_ssc_cfg_tmp = hdmi_ssc_cfg->phy_ssc.ssc_debug_en ? &hdmi_ssc_cfg->phy_ssc.ssc_cfg :
1690 phy_ssc_data_get(hdmi_ssc_cfg->tmds_clk);
1691
1692 hdmi_if_null_return_void(phy_ssc_cfg_tmp);
1693
1694 if ((div_cfg->ssc_byp_div == 0) || (phy_ssc_cfg_tmp->ssc_freq == 0)) {
1695 span_fb = 0;
1696 step_fb = 0;
1697 } else {
1698 /*
1699 * ref_clk calculation
1700 * reference clock = (pixelclk(hz) * pixclkdiv) / ssc_bypass_div
1701 */
1702 phy_ref_clk = hdmi_ssc_cfg->pix_clk * div_cfg->pixel_clk_div * HDMI_THOUSAND;
1703 phy_ref_clk /= div_cfg->ssc_byp_div;
1704 /*
1705 * span fb calculation
1706 * span = ref clock/(ssc_freqence * 4)
1707 */
1708 span_fb = (phy_ref_clk / phy_ssc_cfg_tmp->ssc_freq) / 4; /* 4, according to protocol calculation */
1709 /*
1710 * step fb calculation
1711 * step = (((ssc_amptd * loop_div) / 10000) * ssc_freqcence) / (ref clock / 4)
1712 */
1713 tmp = (div_cfg->loop_div / HDMI_HUNDRED) * phy_ssc_cfg_tmp->ssc_amptd;
1714 tmp = tmp * (phy_ssc_cfg_tmp->ssc_freq / HDMI_THOUSAND);
1715 step_fb = (phy_ref_clk >= 4) ? (tmp / (phy_ref_clk / 4)) : 0; /* 4, (ref clock / 4) is protocol requirements */
1716 }
1717
1718 hdmi_info("ssc info || loop_div:0x%x, ref_clk:%u.\n", div_cfg->loop_div, phy_ref_clk);
1719 hdmi_info(" || amptd:%u, freq:%u, span:0x%x, step:0x%x.\n",
1720 phy_ssc_cfg_tmp->ssc_amptd, phy_ssc_cfg_tmp->ssc_freq, span_fb, step_fb);
1721
1722 hal_hdmi_phy_ssc_on(span_fb, step_fb);
1723 } else {
1724 hal_hdmi_phy_ssc_off(div_cfg->deep_color);
1725 }
1726
1727 /* status info set */
1728 ret = memcpy_s(&g_hdmi_phy_info.ssc_cfg, sizeof(g_hdmi_phy_info.ssc_cfg),
1729 &hdmi_ssc_cfg->phy_ssc, sizeof(hdmi_phy_ssc));
1730 hdmi_unequal_eok_return_void(ret);
1731
1732 return;
1733 }
1734
hal_hdmi_phy_ssc_get(hi_bool * enable)1735 hi_s32 hal_hdmi_phy_ssc_get(hi_bool *enable)
1736 {
1737 hi_u32 span_fb, step_fb;
1738 hi_bool hw_ssc_enable = HI_FALSE;
1739
1740 hdmi_if_fpga_return(HI_SUCCESS);
1741 hdmi_if_null_return(enable, HI_FAILURE);
1742
1743 span_fb = hdmi_reg_step_fb_get();
1744 step_fb = hdmi_reg_span_fb_get();
1745 hw_ssc_enable = ((span_fb == 0) && (step_fb == 0)) ? HI_FALSE : HI_TRUE;
1746 *enable = hw_ssc_enable;
1747
1748 return HI_SUCCESS;
1749 }
1750
hal_hdmi_phy_info_get(hdmi_phy_info * phy_status)1751 hi_s32 hal_hdmi_phy_info_get(hdmi_phy_info *phy_status)
1752 {
1753 errno_t ret;
1754 hdmi_if_fpga_return(HI_SUCCESS);
1755 hdmi_if_null_return(phy_status, HI_FAILURE);
1756
1757 ret = memcpy_s(phy_status, sizeof(hdmi_phy_info), &g_hdmi_phy_info, sizeof(hdmi_phy_info));
1758 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1759
1760 return HI_SUCCESS;
1761 }
1762
hal_hdmi_phy_params_set(hi_u32 tmds_clk,const hdmi_hw_spec * hw_spec)1763 hi_s32 hal_hdmi_phy_params_set(hi_u32 tmds_clk, const hdmi_hw_spec *hw_spec)
1764 {
1765 errno_t ret;
1766 hdmi_device *hdmi_dev = HI_NULL;
1767 hdmi_phy_hw_spec_cfg spec_cfg = {0};
1768
1769 hdmi_if_fpga_return(HI_SUCCESS);
1770 hdmi_if_false_return(g_hdmi_phy_info.init, HI_ERR_HDMI_INVALID_PARA);
1771 hdmi_if_null_return(hw_spec, HI_ERR_NULL_PTR);
1772 hdmi_dev = get_hdmi_device(HDMI_DEVICE_ID0);
1773 hdmi_if_null_return(hdmi_dev, HI_ERR_NULL_PTR);
1774
1775 ret = memcpy_s(&g_hdmi_phy_info.hw_spec.hw_param[0], sizeof(g_hdmi_phy_info.hw_spec.hw_param),
1776 &hw_spec->hw_param[0], sizeof(hdmi_hw_spec));
1777 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1778
1779 spec_cfg.tmds_clk = tmds_clk;
1780 spec_cfg.hdmi_phy_spec.hw_spec_debug_en = HI_FALSE;
1781 spec_cfg.trace_len = hdmi_dev->mode_param.trace_len;
1782 hal_hdmi_phy_spec_set(&spec_cfg);
1783
1784 return HI_SUCCESS;
1785 }
1786
hal_hdmi_phy_params_get(hdmi_phy_hw_param * hw_param)1787 hi_s32 hal_hdmi_phy_params_get(hdmi_phy_hw_param *hw_param)
1788 {
1789 errno_t ret;
1790 hi_u8 i;
1791 hdmi_hw_spec *spec = HI_NULL;
1792
1793 hdmi_if_fpga_return(HI_SUCCESS);
1794 hdmi_if_false_return(g_hdmi_phy_info.init, HI_ERR_NULL_PTR);
1795 hdmi_if_null_return(hw_param, HI_ERR_NULL_PTR);
1796
1797 spec = &hw_param->hw_spec_def;
1798 for (i = 0; i < HDMI_HW_PARAM_NUM; i++) {
1799 #ifndef PHY_CRAFT_S28
1800 spec->hw_param[i].i_de_main_clk = g_phy_hw_spec[i].phy_spec_cfg.i_de_main_clk;
1801 spec->hw_param[i].i_de_main_data = g_phy_hw_spec[i].phy_spec_cfg.i_de_main_d0;
1802 spec->hw_param[i].i_main_clk = g_phy_hw_spec[i].phy_spec_cfg.i_main_clk;
1803 spec->hw_param[i].i_main_data = g_phy_hw_spec[i].phy_spec_cfg.i_main_d0;
1804 #else
1805 spec->hw_param[i].i_de_main_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_clk;
1806 spec->hw_param[i].i_de_main_data = g_hdmi_phy_info.hw_spec.hw_param[i].i_de_main_data;
1807 spec->hw_param[i].i_main_clk = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_clk;
1808 spec->hw_param[i].i_main_data = g_hdmi_phy_info.hw_spec.hw_param[i].i_main_data;
1809 spec->hw_param[i].ft_cap_clk = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_clk;
1810 spec->hw_param[i].ft_cap_data = g_hdmi_phy_info.hw_spec.hw_param[i].ft_cap_data;
1811 #endif
1812 }
1813 ret = memcpy_s(&hw_param->hw_spec_cfg, sizeof(hdmi_hw_spec), &g_hdmi_phy_info.hw_spec, sizeof(hdmi_hw_spec));
1814 hdmi_unequal_eok_return(ret, HI_ERR_HDMI_INVALID_PARA);
1815
1816 phy_cur_hw_param_get(&hw_param->hw_param_cur);
1817
1818 return HI_SUCCESS;
1819 }
1820
1821