1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_product_define.h"
19 #include "hdmi_reg_crg.h"
20 #include "hdmi_reg_dphy.h"
21
22 #define HDMI_IO_CFG_FUNCTION1_SEL 0x1
23
hdmi_tx_reg_write(hi_u32 * reg_addr,hi_u32 value)24 hi_void hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value)
25 {
26 *(volatile hi_u32 *)reg_addr = value;
27 return;
28 }
29
hdmi_tx_reg_read(const hi_u32 * reg_addr)30 hi_u32 hdmi_tx_reg_read(const hi_u32 *reg_addr)
31 {
32 return *(volatile hi_u32 *)(reg_addr);
33 }
34
hdmi_reg_write_u32(hi_u32 reg_addr,hi_u32 value)35 hi_void hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value)
36 {
37 volatile hi_u32 *addr = HI_NULL;
38
39 addr = (volatile hi_u32 *)osal_ioremap_nocache((hi_u64)reg_addr, HDMI_REGISTER_SIZE);
40 if (addr != HI_NULL) {
41 *addr = value;
42 osal_iounmap((void *)addr, HDMI_REGISTER_SIZE);
43 } else {
44 hdmi_err("osal_ioremap_nocache addr=0x%x err!\n", reg_addr);
45 }
46
47 return;
48 }
49
hdmi_reg_read_u32(hi_u32 reg_addr)50 hi_u32 hdmi_reg_read_u32(hi_u32 reg_addr)
51 {
52 volatile hi_u32 *addr = HI_NULL;
53 hi_u32 value = 0;
54
55 addr = (volatile hi_u32 *)osal_ioremap_nocache((hi_u64)reg_addr, HDMI_REGISTER_SIZE);
56 if (addr != HI_NULL) {
57 value = *addr;
58 osal_iounmap((void *)addr, HDMI_REGISTER_SIZE);
59 } else {
60 hdmi_err("osal_ioremap_nocache addr=0x%x\n err!\n", reg_addr);
61 }
62
63 return value;
64 }
65
drv_hdmi_prod_io_cfg_set(hi_void)66 hi_void drv_hdmi_prod_io_cfg_set(hi_void)
67 {
68 /* no IO multiplex */
69 return;
70 }
71
drv_hdmi_prod_crg_gate_set(hi_bool enable)72 hi_void drv_hdmi_prod_crg_gate_set(hi_bool enable)
73 {
74 #ifndef HDMI_FPGA_SUPPORT
75 /* gate */
76 /* crg68 HDMITX_CTRL CRG 0x00110 0x0001043F */
77 hdmi_reg_ssc_in_cken_set(enable);
78 hdmi_reg_ssc_bypass_cken_set(enable);
79 hdmi_reg_ctrl_osc_24m_cken_set(enable);
80 hdmi_reg_ctrl_cec_cken_set(enable);
81 hdmi_reg_ctrl_os_cken_set(enable);
82 hdmi_reg_ctrl_as_cken_set(enable);
83 hdmi_reg_pxl_cken_set(enable);
84 /* crg70 HDMITX_PHY 0x00114 0x00000001 */
85 hdmi_reg_hdmirx_phy_tmds_cken_set(enable);
86 #endif
87
88 return;
89 }
90
drv_hdmi_prod_crg_all_reset_set(hi_bool enable)91 hi_void drv_hdmi_prod_crg_all_reset_set(hi_bool enable)
92 {
93 #ifndef HDMI_FPGA_SUPPORT
94 /* crg68 HDMITX_CTRL CRG 0x00110 0x0001043F */
95 hdmi_reg_ctrl_bus_srst_req_set(enable);
96 hdmi_reg_ctrl_srst_req_set(enable);
97 hdmi_reg_ctrl_cec_srst_req_set(enable);
98 hdmi_reg_ssc_srst_req_set(enable);
99 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
100 hdmi_reg_phy_srst_req_set(enable);
101 hdmi_reg_phy_tmds_srst_req_set(enable);
102 enable = !enable;
103 /* delay 1us, to insure ctrl reset success. */
104 osal_udelay(1);
105 /* crg68 HDMITX_CTRL CRG 0x00110 0x0001043F */
106 hdmi_reg_ctrl_bus_srst_req_set(enable);
107 hdmi_reg_ctrl_srst_req_set(enable);
108 hdmi_reg_ctrl_cec_srst_req_set(enable);
109 hdmi_reg_ssc_srst_req_set(enable);
110 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
111 hdmi_reg_phy_srst_req_set(enable);
112 hdmi_reg_phy_tmds_srst_req_set(enable);
113 /* delay 2us, avoid system crash when start HDMI(no boot) */
114 /* delay 100ms, HPD can not read after reset when enable HPD filtering if not delay. */
115 osal_msleep(100);
116 #endif
117
118 return;
119 }
120
drv_hdmi_hardware_reset(hi_void)121 hi_void drv_hdmi_hardware_reset(hi_void)
122 {
123 #ifndef HDMI_FPGA_SUPPORT
124 if (hdmi_reg_crg_init() != HI_SUCCESS) {
125 hdmi_err("hdmi crg reg init failed!!!!!!!\n");
126 return;
127 }
128 /* crg68 HDMITX_CTRL CRG 0x00110 0x0001043F */
129 hdmi_reg_ctrl_bus_srst_req_set(HI_TRUE);
130 hdmi_reg_ctrl_srst_req_set(HI_TRUE);
131 hdmi_reg_ctrl_cec_srst_req_set(HI_TRUE);
132 hdmi_reg_ssc_srst_req_set(HI_TRUE);
133 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
134 hdmi_reg_phy_srst_req_set(HI_TRUE);
135 hdmi_reg_phy_tmds_srst_req_set(HI_TRUE);
136 /* crg68 HDMITX_CTRL CRG 0x00110 gate */
137 drv_hdmi_prod_crg_gate_set(HI_FALSE);
138 hdmi_reg_crg_deinit();
139 #endif
140
141 return;
142 }
143
drv_hdmi_low_power_set(hi_bool enable)144 hi_void drv_hdmi_low_power_set(hi_bool enable)
145 {
146 hi_unused(enable);
147 return;
148 }
149
drv_hdmi_prod_crg_phy_reset_set(hi_bool enable)150 hi_void drv_hdmi_prod_crg_phy_reset_set(hi_bool enable)
151 {
152 #ifndef HDMI_FPGA_SUPPORT
153 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
154 hdmi_reg_phy_srst_req_set(enable);
155 hdmi_reg_phy_tmds_srst_req_set(enable);
156 enable = !enable;
157 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
158 hdmi_reg_phy_srst_req_set(enable);
159 hdmi_reg_phy_tmds_srst_req_set(enable);
160 #endif
161 return;
162 }
163
drv_hdmi_prod_crg_phy_reset_get(hi_bool * enable)164 hi_void drv_hdmi_prod_crg_phy_reset_get(hi_bool *enable)
165 {
166 #ifndef HDMI_FPGA_SUPPORT
167 hdmi_if_null_return_void(enable);
168
169 /* crg69 HDMITX_PHY 0x00114 0x00000001 */
170 if (hdmi_reg_phy_srst_req_get() || hdmi_reg_phy_tmds_srst_req_get()) {
171 *enable = HI_TRUE;
172 } else {
173 *enable = HI_FALSE;
174 }
175 #endif
176
177 return;
178 }
179
drv_hdmi_prod_crg_div_set(hdmi_crg_cfg * crg_cfg)180 hi_void drv_hdmi_prod_crg_div_set(hdmi_crg_cfg *crg_cfg)
181 {
182 #ifndef HDMI_FPGA_SUPPORT
183 hi_u32 tmp;
184
185 if (crg_cfg != HI_NULL) {
186 tmp = crg_cfg->ssc_bypass_div - 1;
187 hdmi_reg_ssc_clk_div_set(tmp);
188 tmp = crg_cfg->tmds_clk_div - 1;
189 hdmi_reg_tmds_clk_div_set(tmp);
190 /* use phy reg to rest dphy, don't use CRG phy rst reg */
191 hdmi_reg_dphy_rst_set(HI_TRUE);
192 hdmi_reg_dphy_rst_set(HI_FALSE);
193 }
194 #endif
195
196 return;
197 }
198
drv_hdmi_prod_crg_init(hi_void)199 hi_void drv_hdmi_prod_crg_init(hi_void)
200 {
201 #ifndef HDMI_FPGA_SUPPORT
202 drv_hdmi_prod_io_cfg_set();
203 drv_hdmi_prod_crg_gate_set(HI_TRUE);
204 drv_hdmi_prod_crg_all_reset_set(HI_TRUE);
205 #endif
206
207 return;
208 }
209
drv_hdmi_prod_chip_get(hi_void)210 hdmi_chip_type drv_hdmi_prod_chip_get(hi_void)
211 {
212 return CHIP_HI3516CV500;
213 }
214
215