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Searched refs:TargetOpcode (Results 1 – 25 of 206) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp277 case TargetOpcode::G_OR: { in getInstrAlternativeMappings()
300 case TargetOpcode::G_BITCAST: { in getInstrAlternativeMappings()
336 case TargetOpcode::G_LOAD: { in getInstrAlternativeMappings()
373 case TargetOpcode::G_OR: in applyMappingImpl()
374 case TargetOpcode::G_BITCAST: in applyMappingImpl()
375 case TargetOpcode::G_LOAD: in applyMappingImpl()
390 case TargetOpcode::G_FADD: in isPreISelGenericFloatingPointOpcode()
391 case TargetOpcode::G_FSUB: in isPreISelGenericFloatingPointOpcode()
392 case TargetOpcode::G_FMUL: in isPreISelGenericFloatingPointOpcode()
393 case TargetOpcode::G_FMA: in isPreISelGenericFloatingPointOpcode()
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DAArch64InstructionSelector.cpp482 case TargetOpcode::G_SHL: in selectBinaryOp()
484 case TargetOpcode::G_LSHR: in selectBinaryOp()
486 case TargetOpcode::G_ASHR: in selectBinaryOp()
493 case TargetOpcode::G_PTR_ADD: in selectBinaryOp()
495 case TargetOpcode::G_SHL: in selectBinaryOp()
497 case TargetOpcode::G_LSHR: in selectBinaryOp()
499 case TargetOpcode::G_ASHR: in selectBinaryOp()
510 case TargetOpcode::G_FADD: in selectBinaryOp()
512 case TargetOpcode::G_FSUB: in selectBinaryOp()
514 case TargetOpcode::G_FMUL: in selectBinaryOp()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp98 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
111 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
123 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
138 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); in buildConstDbgValue()
158 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
167 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC); in buildDynStackAlloc()
177 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX); in buildFrameIndex()
190 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE); in buildGlobalValue()
198 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {}) in buildJumpTable()
221 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}); in buildPtrAdd()
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DLegalizerHelper.cpp86 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || in legalizeInstrStep()
87 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) in legalizeInstrStep()
242 case TargetOpcode::G_SDIV: in getRTLibDesc()
254 case TargetOpcode::G_UDIV: in getRTLibDesc()
266 case TargetOpcode::G_SREM: in getRTLibDesc()
269 case TargetOpcode::G_UREM: in getRTLibDesc()
272 case TargetOpcode::G_CTLZ_ZERO_UNDEF: in getRTLibDesc()
275 case TargetOpcode::G_FADD: in getRTLibDesc()
278 case TargetOpcode::G_FSUB: in getRTLibDesc()
281 case TargetOpcode::G_FMUL: in getRTLibDesc()
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DGISelKnownBits.cpp44 if (MI.getOpcode() == TargetOpcode::G_FRAME_INDEX) { in inferPtrAlignment()
125 case TargetOpcode::COPY: { in computeKnownBitsImpl()
142 case TargetOpcode::G_CONSTANT: { in computeKnownBitsImpl()
150 case TargetOpcode::G_FRAME_INDEX: { in computeKnownBitsImpl()
154 case TargetOpcode::G_SUB: { in computeKnownBitsImpl()
169 case TargetOpcode::G_XOR: { in computeKnownBitsImpl()
182 case TargetOpcode::G_PTR_ADD: { in computeKnownBitsImpl()
189 case TargetOpcode::G_ADD: { in computeKnownBitsImpl()
210 case TargetOpcode::G_AND: { in computeKnownBitsImpl()
223 case TargetOpcode::G_OR: { in computeKnownBitsImpl()
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DUtils.cpp58 TII.get(TargetOpcode::COPY), ConstrainedReg) in constrainOperandRegClass()
63 TII.get(TargetOpcode::COPY), Reg) in constrainOperandRegClass()
224 return Opcode == TargetOpcode::G_CONSTANT || in getConstantVRegValWithLookThrough()
225 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); in getConstantVRegValWithLookThrough()
247 case TargetOpcode::G_TRUNC: in getConstantVRegValWithLookThrough()
248 case TargetOpcode::G_SEXT: in getConstantVRegValWithLookThrough()
249 case TargetOpcode::G_ZEXT: in getConstantVRegValWithLookThrough()
255 case TargetOpcode::COPY: in getConstantVRegValWithLookThrough()
260 case TargetOpcode::G_INTTOPTR: in getConstantVRegValWithLookThrough()
277 case TargetOpcode::G_TRUNC: in getConstantVRegValWithLookThrough()
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DCombinerHelper.cpp73 if (MI.getOpcode() != TargetOpcode::COPY) in matchCombineCopy()
127 assert(MI.getOpcode() == TargetOpcode::G_CONCAT_VECTORS && in matchCombineConcatVectors()
140 case TargetOpcode::G_BUILD_VECTOR: in matchCombineConcatVectors()
147 case TargetOpcode::G_IMPLICIT_DEF: { in matchCombineConcatVectors()
203 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && in matchCombineShuffleVector()
302 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
314 if (OpcodeForCandidate == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
315 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
317 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
318 OpcodeForCandidate != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
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DCSEInfo.cpp40 case TargetOpcode::G_ADD: in shouldCSEOpc()
41 case TargetOpcode::G_AND: in shouldCSEOpc()
42 case TargetOpcode::G_ASHR: in shouldCSEOpc()
43 case TargetOpcode::G_LSHR: in shouldCSEOpc()
44 case TargetOpcode::G_MUL: in shouldCSEOpc()
45 case TargetOpcode::G_OR: in shouldCSEOpc()
46 case TargetOpcode::G_SHL: in shouldCSEOpc()
47 case TargetOpcode::G_SUB: in shouldCSEOpc()
48 case TargetOpcode::G_XOR: in shouldCSEOpc()
49 case TargetOpcode::G_UDIV: in shouldCSEOpc()
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DCSEMIRBuilder.cpp144 case TargetOpcode::G_ADD: in buildInstr()
145 case TargetOpcode::G_AND: in buildInstr()
146 case TargetOpcode::G_ASHR: in buildInstr()
147 case TargetOpcode::G_LSHR: in buildInstr()
148 case TargetOpcode::G_MUL: in buildInstr()
149 case TargetOpcode::G_OR: in buildInstr()
150 case TargetOpcode::G_SHL: in buildInstr()
151 case TargetOpcode::G_SUB: in buildInstr()
152 case TargetOpcode::G_XOR: in buildInstr()
153 case TargetOpcode::G_UDIV: in buildInstr()
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DIRTranslator.cpp319 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags); in translateFSub()
322 return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); in translateFSub()
333 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags); in translateFNeg()
356 MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1}, in translateCompare()
634 Cond = MIB.buildInstr(TargetOpcode::G_XOR, {i1Ty}, {Cond, True}, None) in emitSwitchCase()
1019 MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]}, in translateSelect()
1043 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder); in translateBitCast()
1174 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD); in getStackGuard()
1208 return TargetOpcode::G_BSWAP; in getSimpleIntrinsicOpcode()
1210 return TargetOpcode::G_BITREVERSE; in getSimpleIntrinsicOpcode()
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DLegalizerInfo.cpp255 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegalizerInfo()
256 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegalizerInfo()
257 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegalizerInfo()
258 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegalizerInfo()
259 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegalizerInfo()
261 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegalizerInfo()
262 setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}}); in LegalizerInfo()
265 TargetOpcode::G_IMPLICIT_DEF, 0, narrowToSmallerAndUnsupportedIfTooSmall); in LegalizerInfo()
267 TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
269 TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h33 case TargetOpcode::G_TRUNC: in isArtifactCast()
34 case TargetOpcode::G_SEXT: in isArtifactCast()
35 case TargetOpcode::G_ZEXT: in isArtifactCast()
36 case TargetOpcode::G_ANYEXT: in isArtifactCast()
51 assert(MI.getOpcode() == TargetOpcode::G_ANYEXT); in tryCombineAnyExt()
83 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineAnyExt()
85 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) { in tryCombineAnyExt()
100 assert(MI.getOpcode() == TargetOpcode::G_ZEXT); in tryCombineZExt()
110 if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || in tryCombineZExt()
127 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineZExt()
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DMIPatternMatch.h194 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
196 return BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>(L, R);
200 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB> m_GSub(const LHS &L,
202 return BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB>(L, R);
206 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>
208 return BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>(L, R);
212 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>
214 return BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>(L, R);
218 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FMUL, true>
220 return BinaryOp_match<LHS, RHS, TargetOpcode::G_FMUL, true>(L, R);
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DConstantFoldingMIRBuilder.h34 case TargetOpcode::G_ADD:
35 case TargetOpcode::G_AND:
36 case TargetOpcode::G_ASHR:
37 case TargetOpcode::G_LSHR:
38 case TargetOpcode::G_MUL:
39 case TargetOpcode::G_OR:
40 case TargetOpcode::G_SHL:
41 case TargetOpcode::G_SUB:
42 case TargetOpcode::G_XOR:
43 case TargetOpcode::G_UDIV:
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DIRTranslator.h354 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); in translateAdd()
357 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); in translateSub()
360 return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder); in translateAnd()
363 return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder); in translateMul()
366 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); in translateOr()
369 return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder); in translateXor()
373 return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder); in translateUDiv()
376 return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder); in translateSDiv()
379 return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder); in translateURem()
382 return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder); in translateSRem()
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DMachineIRBuilder.h524 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
530 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src}); in buildPtrToInt()
535 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src}); in buildIntToPtr()
540 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); in buildBitcast()
545 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src}); in buildAddrSpaceCast()
1229 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1246 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1262 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1268 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1274 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsRegisterBankInfo.cpp111 case TargetOpcode::G_FCONSTANT: in isFloatingPointOpcode()
112 case TargetOpcode::G_FADD: in isFloatingPointOpcode()
113 case TargetOpcode::G_FSUB: in isFloatingPointOpcode()
114 case TargetOpcode::G_FMUL: in isFloatingPointOpcode()
115 case TargetOpcode::G_FDIV: in isFloatingPointOpcode()
116 case TargetOpcode::G_FABS: in isFloatingPointOpcode()
117 case TargetOpcode::G_FSQRT: in isFloatingPointOpcode()
118 case TargetOpcode::G_FCEIL: in isFloatingPointOpcode()
119 case TargetOpcode::G_FFLOOR: in isFloatingPointOpcode()
120 case TargetOpcode::G_FPEXT: in isFloatingPointOpcode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp169 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) { in getInstrMapping()
176 case TargetOpcode::G_ADD: in getInstrMapping()
177 case TargetOpcode::G_SUB: in getInstrMapping()
178 case TargetOpcode::G_MUL: in getInstrMapping()
180 case TargetOpcode::G_FADD: in getInstrMapping()
181 case TargetOpcode::G_FSUB: in getInstrMapping()
182 case TargetOpcode::G_FMUL: in getInstrMapping()
183 case TargetOpcode::G_FDIV: in getInstrMapping()
185 case TargetOpcode::G_SHL: in getInstrMapping()
186 case TargetOpcode::G_LSHR: in getInstrMapping()
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DX86InstructionSelector.cpp255 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectCopy()
320 if (Opcode == TargetOpcode::LOAD_STACK_GUARD) in select()
341 case TargetOpcode::G_STORE: in select()
342 case TargetOpcode::G_LOAD: in select()
344 case TargetOpcode::G_PTR_ADD: in select()
345 case TargetOpcode::G_FRAME_INDEX: in select()
347 case TargetOpcode::G_GLOBAL_VALUE: in select()
349 case TargetOpcode::G_CONSTANT: in select()
351 case TargetOpcode::G_FCONSTANT: in select()
353 case TargetOpcode::G_PTRTOINT: in select()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
52 case TargetOpcode::DBG_LABEL: in doesNotGeneratecode()
63 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); in runOnMachineFunction()
67 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); in runOnMachineFunction()
88 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
DDetectDeadLanes.cpp142 case TargetOpcode::COPY: in lowersToCopies()
143 case TargetOpcode::PHI: in lowersToCopies()
144 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
145 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
146 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
167 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
171 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
176 case TargetOpcode::EXTRACT_SUBREG: { in isCrossCopy()
237 case TargetOpcode::COPY: in transferUsedLanes()
238 case TargetOpcode::PHI: in transferUsedLanes()
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DExpandPostRAPseudos.cpp99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
214 case TargetOpcode::COPY: in runOnMachineFunction()
217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstr.h1039 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1040 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1042 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1051 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1057 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1058 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1080 return getOpcode() == TargetOpcode::PHI ||
1081 getOpcode() == TargetOpcode::G_PHI;
1083 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1084 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGICombiner.inc134 case TargetOpcode::COPY: Partition = 0; break;
135 case TargetOpcode::G_PTR_ADD: Partition = 1; break;
136 case TargetOpcode::G_LOAD: Partition = 2; break;
137 case TargetOpcode::G_SEXTLOAD: Partition = 3; break;
138 case TargetOpcode::G_ZEXTLOAD: Partition = 4; break;
139 case TargetOpcode::G_STORE: Partition = 5; break;
140 case TargetOpcode::G_BR: Partition = 6; break;
144 if (Partition == 0 /* TargetOpcode::COPY */) {
159 if (Partition == 1 /* TargetOpcode::G_PTR_ADD */) {
174 if (Partition == 2 /* TargetOpcode::G_LOAD */) {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
194 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddOperand()
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
494 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
542 TII->get(TargetOpcode::COPY), VRBase); in EmitSubregNode()
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