| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86Instr3DNow.td | 92 let SchedRW = [WriteLoad] in {
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| D | X86InstrInfo.td | 1250 let mayLoad = 1, SchedRW = [WriteLoad] in {
1332 SchedRW = [WriteLoad] in {
1346 let mayLoad = 1, SchedRW = [WriteLoad] in {
1385 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1391 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1735 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1784 Sched<[WriteLoad]>;
2238 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>;
2846 let SchedRW = [WriteLoad] in {
2967 let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
[all …]
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| D | X86InstrFPStack.td | 474 let SchedRW = [WriteLoad], Uses = [FPCW] in {
548 let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {
713 Sched<[WriteLoad]>;
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| D | X86Schedule.td | 124 def WriteLoad : SchedWrite;
128 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
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| D | X86ScheduleSLM.td | 88 def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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| D | X86ScheduleBdVer2.td | 268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
274 // FIXME: These are copy and pasted from WriteLoad/Store.
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| D | X86ScheduleZnver2.td | 179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 8; }
512 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
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| D | X86ScheduleZnver1.td | 180 def : WriteRes<WriteLoad, [ZnAGU]> { let Latency = 8; }
530 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
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| D | X86ScheduleAtom.td | 167 def : WriteRes<WriteLoad, [AtomPort0]>;
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| D | X86ScheduleBtVer2.td | 272 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 3; }
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| D | X86SchedSandyBridge.td | 112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
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| D | X86SchedBroadwell.td | 204 defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>;
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| D | X86SchedSkylakeClient.td | 201 defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>;
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| D | X86SchedHaswell.td | 124 defm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>;
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| D | X86SchedSkylakeServer.td | 201 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
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| D | X86InstrSSE.td | 3160 let Predicates = [HasSSEPrefetch], SchedRW = [WriteLoad] in {
3172 let SchedRW = [WriteLoad] in {
7919 VEX, Sched<[WriteLoad]>;
7927 VEX, VEX_L, Sched<[WriteLoad]>;
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| D | X86InstrCompiler.td | 674 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
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| D | X86InstrAVX512.td | 2810 Sched<[WriteLoad]>;
9600 EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteLoad]>;
9712 EVEX, EVEX_K, Sched<[WriteLoad]>;
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| /third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/ |
| D | glslang_wrapper_utils.cpp | 1781 spirv::WriteLoad(blobOut, tempVarType, tempVar, mFixedVaryingId[id], nullptr); in writeInputPreamble()
1829 spirv::WriteLoad(blobOut, tempVarType, tempVar, id, nullptr); in writeOutputPrologue()
2555 spirv::WriteLoad(blobOut, mIVec4Id, xfbOffsets, xfbOffsetsVar, nullptr); in writeGetOffsetsCall()
2585 spirv::WriteLoad(blobOut, varyingTypeId, component, loadPtr, nullptr); in writeComponentCapture()
3199 spirv::WriteLoad(mSpirvBlobOut, mIds.vec4Id(), positionId, positionPointerId, nullptr); in writeOutputPrologue()
4416 spirv::WriteLoad(mSpirvBlobOut, replacementTypeId, loadResultId, replacementId, nullptr); in transformLoadHelper()
4479 spirv::WriteLoad(mSpirvBlobOut, replacementTypeId, id, pointerId, nullptr); in transformLoad()
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| /third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/vulkan/ |
| D | UtilsVk.cpp | 862 spirv::WriteLoad(blobOut, loadType, loadResult, inId, nullptr); in InsertColorUnresolveLoadStore()
884 spirv::WriteLoad(blobOut, loadType, loadResult, inId, nullptr); in InsertDepthStencilUnresolveLoadStore()
906 spirv::WriteLoad(blobOut, loadType, loadResult, inId, nullptr); in InsertDepthStencilUnresolveLoadStore()
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| /third_party/skia/third_party/externals/angle2/src/common/spirv/ |
| D | spirv_instruction_builder_autogen.h | 131 void WriteLoad(Blob *blob,
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| D | spirv_instruction_builder_autogen.cpp | 584 void WriteLoad(Blob *blob, in WriteLoad() function
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| /third_party/skia/third_party/externals/angle2/src/compiler/translator/ |
| D | OutputSPIRV.cpp | 946 spirv::WriteLoad(mBuilder.getSpirvCurrentFunctionBlock(), in accessChainLoad()
956 spirv::WriteLoad(mBuilder.getSpirvCurrentFunctionBlock(), accessChain.preSwizzleTypeId, in accessChainLoad()
1029 spirv::WriteLoad(mBuilder.getSpirvCurrentFunctionBlock(), accessChain.preSwizzleTypeId, in accessChainStore()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 5751 {DBGFIELD("WriteLoad") 1, false, false, 6, 2, 1, 1, 0, 0}, // #62
7128 {DBGFIELD("WriteLoad") 1, false, false, 169, 2, 6, 1, 0, 0}, // #62
8505 {DBGFIELD("WriteLoad") 1, false, false, 745, 3, 6, 1, 0, 0}, // #62
9882 {DBGFIELD("WriteLoad") 1, false, false, 709, 2, 22, 1, 0, 0}, // #62
11259 {DBGFIELD("WriteLoad") 1, false, false, 745, 3, 6, 1, 0, 0}, // #62
12636 {DBGFIELD("WriteLoad") 1, false, false, 3714, 2, 6, 1, 0, 0}, // #62
14013 {DBGFIELD("WriteLoad") 1, false, false, 745, 3, 6, 1, 0, 0}, // #62
15390 {DBGFIELD("WriteLoad") 1, false, false, 129, 1, 22, 1, 0, 0}, // #62
16767 {DBGFIELD("WriteLoad") 1, false, false, 745, 3, 6, 1, 0, 0}, // #62
18144 {DBGFIELD("WriteLoad") 1, false, false, 2, 1, 11, 1, 0, 0}, // #62
[all …]
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| D | X86GenInstrInfo.inc | 15339 WriteLoad = 62,
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