1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "../../../../../include/dt-bindings/clock/rk3588-cru.h" 7#include "../../../../..//include/dt-bindings/interrupt-controller/arm-gic.h" 8#include "../../../../../include/dt-bindings/interrupt-controller/irq.h" 9#include "../../../../../include/dt-bindings/phy/phy.h" 10#include "../../../../../include/dt-bindings/power/rk3588-power.h" 11#include "../../../../../include/dt-bindings/soc/rockchip,boot-mode.h" 12#include "../../../../../include/dt-bindings/soc/rockchip-system-status.h" 13#include "../../../../../include/dt-bindings/suspend/rockchip-rk3588.h" 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 csi2dcphy0 = &csi2_dcphy0; 24 csi2dcphy1 = &csi2_dcphy1; 25 csi2dphy0 = &csi2_dphy0; 26 csi2dphy1 = &csi2_dphy1; 27 csi2dphy2 = &csi2_dphy2; 28 dsi0 = &dsi0; 29 dsi1 = &dsi1; 30 ethernet1 = &gmac1; 31 gpio0 = &gpio0; 32 gpio1 = &gpio1; 33 gpio2 = &gpio2; 34 gpio3 = &gpio3; 35 gpio4 = &gpio4; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 rkcif_mipi_lvds0= &rkcif_mipi_lvds; 46 rkcif_mipi_lvds1= &rkcif_mipi_lvds1; 47 rkcif_mipi_lvds2= &rkcif_mipi_lvds2; 48 rkcif_mipi_lvds3= &rkcif_mipi_lvds3; 49 rkvenc0 = &rkvenc0; 50 rkvenc1 = &rkvenc1; 51 jpege0 = &jpege0; 52 jpege1 = &jpege1; 53 jpege2 = &jpege2; 54 jpege3 = &jpege3; 55 serial0 = &uart0; 56 serial1 = &uart1; 57 serial2 = &uart2; 58 serial3 = &uart3; 59 serial4 = &uart4; 60 serial5 = &uart5; 61 serial6 = &uart6; 62 serial7 = &uart7; 63 serial8 = &uart8; 64 serial9 = &uart9; 65 spi0 = &spi0; 66 spi1 = &spi1; 67 spi2 = &spi2; 68 spi3 = &spi3; 69 spi4 = &spi4; 70 spi5 = &sfc; 71 }; 72 73 clocks { 74 compatible = "simple-bus"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 spll: spll { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <702000000>; 83 clock-output-names = "spll"; 84 }; 85 86 xin32k: xin32k { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <32768>; 90 clock-output-names = "xin32k"; 91 }; 92 93 xin24m: xin24m { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <24000000>; 97 clock-output-names = "xin24m"; 98 }; 99 100 hclk_vo1: hclk_vo1@fd7c08ec { 101 compatible = "rockchip,rk3588-clock-gate-link"; 102 reg = <0 0xfd7c08ec 0 0x10>; 103 clock-names = "link"; 104 clocks = <&cru HCLK_VO1USB_TOP_ROOT>; 105 #power-domain-cells = <1>; 106 #clock-cells = <0>; 107 }; 108 109 aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 { 110 compatible = "rockchip,rk3588-clock-gate-link"; 111 reg = <0 0xfd7c08b0 0 0x10>; 112 clock-names = "link"; 113 clocks = <&cru ACLK_VDPU_ROOT>; 114 #power-domain-cells = <1>; 115 #clock-cells = <0>; 116 }; 117 118 hclk_vo0: hclk_vo0@fd7c08dc { 119 compatible = "rockchip,rk3588-clock-gate-link"; 120 reg = <0 0xfd7c08dc 0 0x10>; 121 clock-names = "link"; 122 clocks = <&cru HCLK_VOP_ROOT>; 123 #power-domain-cells = <1>; 124 #clock-cells = <0>; 125 }; 126 127 hclk_usb: hclk_usb@fd7c08a8 { 128 compatible = "rockchip,rk3588-clock-gate-link"; 129 reg = <0 0xfd7c08a8 0 0x10>; 130 clock-names = "link"; 131 clocks = <&cru HCLK_VO1USB_TOP_ROOT>; 132 #power-domain-cells = <1>; 133 #clock-cells = <0>; 134 }; 135 136 hclk_nvm: hclk_nvm@fd7c087c { 137 compatible = "rockchip,rk3588-clock-gate-link"; 138 reg = <0 0xfd7c087c 0 0x10>; 139 clock-names = "link"; 140 clocks = <&cru ACLK_NVM_ROOT>; 141 #power-domain-cells = <1>; 142 #clock-cells = <0>; 143 }; 144 145 aclk_usb: aclk_usb@fd7c08a8 { 146 compatible = "rockchip,rk3588-clock-gate-link"; 147 reg = <0 0xfd7c08a8 0 0x10>; 148 clock-names = "link"; 149 clocks = <&cru ACLK_VO1USB_TOP_ROOT>; 150 #power-domain-cells = <1>; 151 #clock-cells = <0>; 152 }; 153 154 hclk_isp1_pre: hclk_isp1_pre@fd7c0868 { 155 compatible = "rockchip,rk3588-clock-gate-link"; 156 reg = <0 0xfd7c0868 0 0x10>; 157 clock-names = "link"; 158 clocks = <&cru HCLK_VI_ROOT>; 159 #power-domain-cells = <1>; 160 #clock-cells = <0>; 161 }; 162 163 aclk_isp1_pre: aclk_isp1_pre@fd7c0868 { 164 compatible = "rockchip,rk3588-clock-gate-link"; 165 reg = <0 0xfd7c0868 0 0x10>; 166 clock-names = "link"; 167 clocks = <&cru ACLK_VI_ROOT>; 168 #power-domain-cells = <1>; 169 #clock-cells = <0>; 170 }; 171 172 aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 { 173 compatible = "rockchip,rk3588-clock-gate-link"; 174 reg = <0 0xfd7c08a0 0 0x10>; 175 clock-names = "link"; 176 clocks = <&cru ACLK_VDPU_ROOT>; 177 #power-domain-cells = <1>; 178 #clock-cells = <0>; 179 }; 180 181 hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 { 182 compatible = "rockchip,rk3588-clock-gate-link"; 183 reg = <0 0xfd7c08a0 0 0x10>; 184 clock-names = "link"; 185 clocks = <&cru HCLK_VDPU_ROOT>; 186 #power-domain-cells = <1>; 187 #clock-cells = <0>; 188 }; 189 190 aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 { 191 compatible = "rockchip,rk3588-clock-gate-link"; 192 reg = <0 0xfd7c08a4 0 0x10>; 193 clock-names = "link"; 194 clocks = <&cru ACLK_VDPU_ROOT>; 195 #power-domain-cells = <1>; 196 #clock-cells = <0>; 197 }; 198 199 hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 { 200 compatible = "rockchip,rk3588-clock-gate-link"; 201 reg = <0 0xfd7c08a4 0 0x10>; 202 clock-names = "link"; 203 clocks = <&cru HCLK_VDPU_ROOT>; 204 #power-domain-cells = <1>; 205 #clock-cells = <0>; 206 }; 207 208 aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 { 209 compatible = "rockchip,rk3588-clock-gate-link"; 210 reg = <0 0xfd7c08b0 0 0x10>; 211 clock-names = "link"; 212 clocks = <&cru ACLK_VDPU_ROOT>; 213 #power-domain-cells = <1>; 214 #clock-cells = <0>; 215 }; 216 217 aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 { 218 compatible = "rockchip,rk3588-clock-gate-link"; 219 reg = <0 0xfd7c08c0 0 0x10>; 220 clock-names = "link"; 221 clocks = <&cru ACLK_RKVENC0>; 222 #power-domain-cells = <1>; 223 #clock-cells = <0>; 224 }; 225 226 hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 { 227 compatible = "rockchip,rk3588-clock-gate-link"; 228 reg = <0 0xfd7c08c0 0 0x10>; 229 clock-names = "link"; 230 clocks = <&cru HCLK_RKVENC0>; 231 #power-domain-cells = <1>; 232 #clock-cells = <0>; 233 }; 234 235 aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc { 236 compatible = "rockchip,rk3588-clock-gate-link"; 237 reg = <0 0xfd7c08dc 0 0x10>; 238 clock-names = "link"; 239 clocks = <&cru ACLK_VOP_LOW_ROOT>; 240 #power-domain-cells = <1>; 241 #clock-cells = <0>; 242 }; 243 244 aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec { 245 compatible = "rockchip,rk3588-clock-gate-link"; 246 reg = <0 0xfd7c08ec 0 0x10>; 247 clock-names = "link"; 248 clocks = <&cru ACLK_VO1USB_TOP_ROOT>; 249 #power-domain-cells = <1>; 250 #clock-cells = <0>; 251 }; 252 253 pclk_av1_pre: pclk_av1_pre@fd7c0910 { 254 compatible = "rockchip,rk3588-clock-gate-link"; 255 reg = <0 0xfd7c0910 0 0x10>; 256 clock-names = "link"; 257 clocks = <&cru HCLK_VDPU_ROOT>; 258 #power-domain-cells = <1>; 259 #clock-cells = <0>; 260 }; 261 262 aclk_av1_pre: aclk_av1_pre@fd7c0910 { 263 compatible = "rockchip,rk3588-clock-gate-link"; 264 reg = <0 0xfd7c0910 0 0x10>; 265 clock-names = "link"; 266 clocks = <&cru ACLK_VDPU_ROOT>; 267 #power-domain-cells = <1>; 268 #clock-cells = <0>; 269 }; 270 271 hclk_sdio_pre: hclk_sdio_pre@fd7c092c { 272 compatible = "rockchip,rk3588-clock-gate-link"; 273 reg = <0 0xfd7c092c 0 0x10>; 274 clock-names = "link"; 275 clocks = <&hclk_nvm>; 276 #power-domain-cells = <1>; 277 #clock-cells = <0>; 278 }; 279 }; 280 281 cpus { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 285 cpu-map { 286 cluster0 { 287 core0 { 288 cpu = <&cpu_l0>; 289 }; 290 core1 { 291 cpu = <&cpu_l1>; 292 }; 293 core2 { 294 cpu = <&cpu_l2>; 295 }; 296 core3 { 297 cpu = <&cpu_l3>; 298 }; 299 }; 300 cluster1 { 301 core0 { 302 cpu = <&cpu_b0>; 303 }; 304 core1 { 305 cpu = <&cpu_b1>; 306 }; 307 }; 308 cluster2 { 309 core0 { 310 cpu = <&cpu_b2>; 311 }; 312 core1 { 313 cpu = <&cpu_b3>; 314 }; 315 }; 316 }; 317 318 cpu_l0: cpu@0 { 319 device_type = "cpu"; 320 compatible = "arm,cortex-a55"; 321 reg = <0x0>; 322 enable-method = "psci"; 323 capacity-dmips-mhz = <530>; 324 clocks = <&scmi_clk SCMI_CLK_CPUL>; 325 operating-points-v2 = <&cluster0_opp_table>; 326 cpu-idle-states = <&CPU_SLEEP>; 327 i-cache-size = <32768>; 328 i-cache-line-size = <64>; 329 i-cache-sets = <128>; 330 d-cache-size = <32768>; 331 d-cache-line-size = <64>; 332 d-cache-sets = <128>; 333 next-level-cache = <&l2_cache_l0>; 334 }; 335 336 cpu_l1: cpu@100 { 337 device_type = "cpu"; 338 compatible = "arm,cortex-a55"; 339 reg = <0x100>; 340 enable-method = "psci"; 341 capacity-dmips-mhz = <530>; 342 clocks = <&scmi_clk SCMI_CLK_CPUL>; 343 operating-points-v2 = <&cluster0_opp_table>; 344 cpu-idle-states = <&CPU_SLEEP>; 345 i-cache-size = <32768>; 346 i-cache-line-size = <64>; 347 i-cache-sets = <128>; 348 d-cache-size = <32768>; 349 d-cache-line-size = <64>; 350 d-cache-sets = <128>; 351 next-level-cache = <&l2_cache_l1>; 352 }; 353 354 cpu_l2: cpu@200 { 355 device_type = "cpu"; 356 compatible = "arm,cortex-a55"; 357 reg = <0x200>; 358 enable-method = "psci"; 359 capacity-dmips-mhz = <530>; 360 clocks = <&scmi_clk SCMI_CLK_CPUL>; 361 operating-points-v2 = <&cluster0_opp_table>; 362 cpu-idle-states = <&CPU_SLEEP>; 363 i-cache-size = <32768>; 364 i-cache-line-size = <64>; 365 i-cache-sets = <128>; 366 d-cache-size = <32768>; 367 d-cache-line-size = <64>; 368 d-cache-sets = <128>; 369 next-level-cache = <&l2_cache_l2>; 370 }; 371 372 cpu_l3: cpu@300 { 373 device_type = "cpu"; 374 compatible = "arm,cortex-a55"; 375 reg = <0x300>; 376 enable-method = "psci"; 377 capacity-dmips-mhz = <530>; 378 clocks = <&scmi_clk SCMI_CLK_CPUL>; 379 operating-points-v2 = <&cluster0_opp_table>; 380 cpu-idle-states = <&CPU_SLEEP>; 381 i-cache-size = <32768>; 382 i-cache-line-size = <64>; 383 i-cache-sets = <128>; 384 d-cache-size = <32768>; 385 d-cache-line-size = <64>; 386 d-cache-sets = <128>; 387 next-level-cache = <&l2_cache_l3>; 388 }; 389 390 cpu_b0: cpu@400 { 391 device_type = "cpu"; 392 compatible = "arm,cortex-a76"; 393 reg = <0x400>; 394 enable-method = "psci"; 395 capacity-dmips-mhz = <1024>; 396 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 397 operating-points-v2 = <&cluster1_opp_table>; 398 cpu-idle-states = <&CPU_SLEEP>; 399 i-cache-size = <65536>; 400 i-cache-line-size = <64>; 401 i-cache-sets = <256>; 402 d-cache-size = <65536>; 403 d-cache-line-size = <64>; 404 d-cache-sets = <256>; 405 next-level-cache = <&l2_cache_b0>; 406 }; 407 408 cpu_b1: cpu@500 { 409 device_type = "cpu"; 410 compatible = "arm,cortex-a76"; 411 reg = <0x500>; 412 enable-method = "psci"; 413 capacity-dmips-mhz = <1024>; 414 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 415 operating-points-v2 = <&cluster1_opp_table>; 416 cpu-idle-states = <&CPU_SLEEP>; 417 i-cache-size = <65536>; 418 i-cache-line-size = <64>; 419 i-cache-sets = <256>; 420 d-cache-size = <65536>; 421 d-cache-line-size = <64>; 422 d-cache-sets = <256>; 423 next-level-cache = <&l2_cache_b1>; 424 }; 425 426 cpu_b2: cpu@600 { 427 device_type = "cpu"; 428 compatible = "arm,cortex-a76"; 429 reg = <0x600>; 430 enable-method = "psci"; 431 capacity-dmips-mhz = <1024>; 432 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 433 operating-points-v2 = <&cluster2_opp_table>; 434 cpu-idle-states = <&CPU_SLEEP>; 435 i-cache-size = <65536>; 436 i-cache-line-size = <64>; 437 i-cache-sets = <256>; 438 d-cache-size = <65536>; 439 d-cache-line-size = <64>; 440 d-cache-sets = <256>; 441 next-level-cache = <&l2_cache_b2>; 442 }; 443 444 cpu_b3: cpu@700 { 445 device_type = "cpu"; 446 compatible = "arm,cortex-a76"; 447 reg = <0x700>; 448 enable-method = "psci"; 449 capacity-dmips-mhz = <1024>; 450 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 451 operating-points-v2 = <&cluster2_opp_table>; 452 cpu-idle-states = <&CPU_SLEEP>; 453 i-cache-size = <65536>; 454 i-cache-line-size = <64>; 455 i-cache-sets = <256>; 456 d-cache-size = <65536>; 457 d-cache-line-size = <64>; 458 d-cache-sets = <256>; 459 next-level-cache = <&l2_cache_b3>; 460 }; 461 462 idle-states { 463 entry-method = "psci"; 464 CPU_SLEEP: cpu-sleep { 465 compatible = "arm,idle-state"; 466 local-timer-stop; 467 arm,psci-suspend-param = <0x0010000>; 468 entry-latency-us = <100>; 469 exit-latency-us = <120>; 470 min-residency-us = <1000>; 471 status = "disabled"; 472 }; 473 }; 474 475 l2_cache_l0: l2-cache-l0 { 476 compatible = "cache"; 477 cache-size = <131072>; 478 cache-line-size = <64>; 479 cache-sets = <512>; 480 next-level-cache = <&l3_cache>; 481 }; 482 483 l2_cache_l1: l2-cache-l1 { 484 compatible = "cache"; 485 cache-size = <131072>; 486 cache-line-size = <64>; 487 cache-sets = <512>; 488 next-level-cache = <&l3_cache>; 489 }; 490 491 l2_cache_l2: l2-cache-l2 { 492 compatible = "cache"; 493 cache-size = <131072>; 494 cache-line-size = <64>; 495 cache-sets = <512>; 496 next-level-cache = <&l3_cache>; 497 }; 498 499 l2_cache_l3: l2-cache-l3 { 500 compatible = "cache"; 501 cache-size = <131072>; 502 cache-line-size = <64>; 503 cache-sets = <512>; 504 next-level-cache = <&l3_cache>; 505 }; 506 507 l2_cache_b0: l2-cache-b0 { 508 compatible = "cache"; 509 cache-size = <524288>; 510 cache-line-size = <64>; 511 cache-sets = <1024>; 512 next-level-cache = <&l3_cache>; 513 }; 514 515 l2_cache_b1: l2-cache-b1 { 516 compatible = "cache"; 517 cache-size = <524288>; 518 cache-line-size = <64>; 519 cache-sets = <1024>; 520 next-level-cache = <&l3_cache>; 521 }; 522 523 l2_cache_b2: l2-cache-b2 { 524 compatible = "cache"; 525 cache-size = <524288>; 526 cache-line-size = <64>; 527 cache-sets = <1024>; 528 next-level-cache = <&l3_cache>; 529 }; 530 531 l2_cache_b3: l2-cache-b3 { 532 compatible = "cache"; 533 cache-size = <524288>; 534 cache-line-size = <64>; 535 cache-sets = <1024>; 536 next-level-cache = <&l3_cache>; 537 }; 538 539 l3_cache: l3-cache { 540 compatible = "cache"; 541 cache-size = <3145728>; 542 cache-line-size = <64>; 543 cache-sets = <4096>; 544 }; 545 }; 546 547 cluster0_opp_table: cluster0-opp-table { 548 compatible = "operating-points-v2"; 549 opp-shared; 550 551 opp-408000000 { 552 opp-hz = /bits/ 64 <408000000>; 553 opp-microvolt = <750000 750000 950000>, 554 <750000 750000 950000>; 555 clock-latency-ns = <40000>; 556 opp-suspend; 557 }; 558 opp-600000000 { 559 opp-hz = /bits/ 64 <600000000>; 560 opp-microvolt = <750000 750000 950000>, 561 <750000 750000 950000>; 562 clock-latency-ns = <40000>; 563 }; 564 opp-816000000 { 565 opp-hz = /bits/ 64 <816000000>; 566 opp-microvolt = <750000 750000 950000>, 567 <750000 750000 950000>; 568 clock-latency-ns = <40000>; 569 }; 570 opp-1008000000 { 571 opp-hz = /bits/ 64 <1008000000>; 572 opp-microvolt = <750000 750000 950000>, 573 <750000 750000 950000>; 574 clock-latency-ns = <40000>; 575 }; 576 opp-1200000000 { 577 opp-hz = /bits/ 64 <1200000000>; 578 opp-microvolt = <775000 775000 950000>, 579 <775000 775000 950000>; 580 clock-latency-ns = <40000>; 581 }; 582 opp-1416000000 { 583 opp-hz = /bits/ 64 <1416000000>; 584 opp-microvolt = <825000 825000 950000>, 585 <825000 825000 950000>; 586 clock-latency-ns = <40000>; 587 }; 588 opp-1608000000 { 589 opp-hz = /bits/ 64 <1608000000>; 590 opp-microvolt = <875000 875000 950000>, 591 <875000 875000 950000>; 592 clock-latency-ns = <40000>; 593 }; 594 opp-1800000000 { 595 opp-hz = /bits/ 64 <1800000000>; 596 opp-microvolt = <950000 950000 950000>, 597 <950000 950000 950000>; 598 clock-latency-ns = <40000>; 599 }; 600 }; 601 602 cluster1_opp_table: cluster1-opp-table { 603 compatible = "operating-points-v2"; 604 opp-shared; 605 606 rockchip,grf = <&bigcore0_grf>; 607 volt-mem-read-margin = < 608 855000 1 609 765000 2 610 675000 3 611 495000 4 612 >; 613 614 rockchip,reboot-freq = <1800000>; 615 616 opp-408000000 { 617 opp-hz = /bits/ 64 <408000000>; 618 opp-microvolt = <600000 600000 1000000>, 619 <675000 675000 1000000>; 620 clock-latency-ns = <40000>; 621 opp-suspend; 622 }; 623 opp-600000000 { 624 opp-hz = /bits/ 64 <600000000>; 625 opp-microvolt = <600000 600000 1000000>, 626 <675000 675000 1000000>; 627 clock-latency-ns = <40000>; 628 }; 629 opp-816000000 { 630 opp-hz = /bits/ 64 <816000000>; 631 opp-microvolt = <600000 600000 1000000>, 632 <675000 675000 1000000>; 633 clock-latency-ns = <40000>; 634 }; 635 opp-1008000000 { 636 opp-hz = /bits/ 64 <1008000000>; 637 opp-microvolt = <625000 625000 1000000>, 638 <675000 675000 1000000>; 639 clock-latency-ns = <40000>; 640 }; 641 opp-1200000000 { 642 opp-hz = /bits/ 64 <1200000000>; 643 opp-microvolt = <650000 650000 1000000>, 644 <675000 675000 1000000>; 645 clock-latency-ns = <40000>; 646 }; 647 opp-1416000000 { 648 opp-hz = /bits/ 64 <1416000000>; 649 opp-microvolt = <675000 675000 1000000>, 650 <675000 675000 1000000>; 651 clock-latency-ns = <40000>; 652 }; 653 opp-1608000000 { 654 opp-hz = /bits/ 64 <1608000000>; 655 opp-microvolt = <700000 700000 1000000>, 656 <700000 700000 1000000>; 657 clock-latency-ns = <40000>; 658 }; 659 opp-1800000000 { 660 opp-hz = /bits/ 64 <1800000000>; 661 opp-microvolt = <775000 775000 1000000>, 662 <775000 775000 1000000>; 663 clock-latency-ns = <40000>; 664 }; 665 opp-2016000000 { 666 opp-hz = /bits/ 64 <2016000000>; 667 opp-microvolt = <850000 850000 1000000>, 668 <850000 850000 1000000>; 669 clock-latency-ns = <40000>; 670 }; 671 opp-2208000000 { 672 opp-hz = /bits/ 64 <2208000000>; 673 opp-microvolt = <925000 925000 1000000>, 674 <925000 925000 1000000>; 675 clock-latency-ns = <40000>; 676 }; 677 opp-2400000000 { 678 opp-hz = /bits/ 64 <2400000000>; 679 opp-microvolt = <1000000 1000000 1000000>, 680 <1000000 1000000 1000000>; 681 clock-latency-ns = <40000>; 682 }; 683 }; 684 685 cluster2_opp_table: cluster2-opp-table { 686 compatible = "operating-points-v2"; 687 opp-shared; 688 689 rockchip,grf = <&bigcore1_grf>; 690 volt-mem-read-margin = < 691 855000 1 692 765000 2 693 675000 3 694 495000 4 695 >; 696 697 rockchip,reboot-freq = <1800000>; 698 699 opp-408000000 { 700 opp-hz = /bits/ 64 <408000000>; 701 opp-microvolt = <600000 600000 1000000>, 702 <675000 675000 1000000>; 703 clock-latency-ns = <40000>; 704 opp-suspend; 705 }; 706 opp-600000000 { 707 opp-hz = /bits/ 64 <600000000>; 708 opp-microvolt = <600000 600000 1000000>, 709 <675000 675000 1000000>; 710 clock-latency-ns = <40000>; 711 }; 712 opp-816000000 { 713 opp-hz = /bits/ 64 <816000000>; 714 opp-microvolt = <600000 600000 1000000>, 715 <675000 675000 1000000>; 716 clock-latency-ns = <40000>; 717 }; 718 opp-1008000000 { 719 opp-hz = /bits/ 64 <1008000000>; 720 opp-microvolt = <625000 625000 1000000>, 721 <675000 675000 1000000>; 722 clock-latency-ns = <40000>; 723 }; 724 opp-1200000000 { 725 opp-hz = /bits/ 64 <1200000000>; 726 opp-microvolt = <650000 650000 1000000>, 727 <675000 675000 1000000>; 728 clock-latency-ns = <40000>; 729 }; 730 opp-1416000000 { 731 opp-hz = /bits/ 64 <1416000000>; 732 opp-microvolt = <675000 675000 1000000>, 733 <675000 675000 1000000>; 734 clock-latency-ns = <40000>; 735 }; 736 opp-1608000000 { 737 opp-hz = /bits/ 64 <1608000000>; 738 opp-microvolt = <700000 700000 1000000>, 739 <700000 700000 1000000>; 740 clock-latency-ns = <40000>; 741 }; 742 opp-1800000000 { 743 opp-hz = /bits/ 64 <1800000000>; 744 opp-microvolt = <775000 775000 1000000>, 745 <775000 775000 1000000>; 746 clock-latency-ns = <40000>; 747 }; 748 opp-2016000000 { 749 opp-hz = /bits/ 64 <2016000000>; 750 opp-microvolt = <850000 850000 1000000>, 751 <850000 850000 1000000>; 752 clock-latency-ns = <40000>; 753 }; 754 opp-2208000000 { 755 opp-hz = /bits/ 64 <2208000000>; 756 opp-microvolt = <925000 925000 1000000>, 757 <925000 925000 1000000>; 758 clock-latency-ns = <40000>; 759 }; 760 opp-2400000000 { 761 opp-hz = /bits/ 64 <2400000000>; 762 opp-microvolt = <1000000 1000000 1000000>, 763 <1000000 1000000 1000000>; 764 clock-latency-ns = <40000>; 765 }; 766 }; 767 768 arm_pmu: arm-pmu { 769 compatible = "arm,armv8-pmuv3"; 770 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 771 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 772 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 773 }; 774 775 cpuinfo { 776 compatible = "rockchip,cpuinfo"; 777 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 778 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 779 }; 780 781 csi2_dcphy0: csi2-dcphy0 { 782 compatible = "rockchip,rk3588-csi2-dcphy"; 783 rockchip,hw = <&csi2_dcphy0_hw>; 784 status = "disabled"; 785 }; 786 787 csi2_dcphy1: csi2-dcphy1 { 788 compatible = "rockchip,rk3588-csi2-dcphy"; 789 rockchip,hw = <&csi2_dcphy1_hw>; 790 status = "disabled"; 791 }; 792 793 /* dphy0 full mode */ 794 csi2_dphy0: csi2-dphy0 { 795 compatible = "rockchip,rk3568-csi2-dphy"; 796 rockchip,hw = <&csi2_dphy0_hw>; 797 status = "disabled"; 798 }; 799 800 /* dphy0 split mode 01 */ 801 csi2_dphy1: csi2-dphy1 { 802 compatible = "rockchip,rk3568-csi2-dphy"; 803 rockchip,hw = <&csi2_dphy0_hw>; 804 status = "disabled"; 805 }; 806 807 /* dphy0 split mode 23 */ 808 csi2_dphy2: csi2-dphy2 { 809 compatible = "rockchip,rk3568-csi2-dphy"; 810 rockchip,hw = <&csi2_dphy0_hw>; 811 status = "disabled"; 812 }; 813 814 display_subsystem: display-subsystem { 815 compatible = "rockchip,display-subsystem"; 816 ports = <&vop_out>; 817 818 route { 819 route_dp0: route-dp0 { 820 status = "disabled"; 821 logo,uboot = "logo.bmp"; 822 logo,kernel = "logo_kernel.bmp"; 823 logo,mode = "center"; 824 charge_logo,mode = "center"; 825 connect = <&vp1_out_dp0>; 826 }; 827 828 route_dsi0: route-dsi0 { 829 status = "disabled"; 830 logo,uboot = "logo.bmp"; 831 logo,kernel = "logo_kernel.bmp"; 832 logo,mode = "center"; 833 charge_logo,mode = "center"; 834 connect = <&vp3_out_dsi0>; 835 }; 836 837 route_dsi1: route-dsi1 { 838 status = "disabled"; 839 logo,uboot = "logo.bmp"; 840 logo,kernel = "logo_kernel.bmp"; 841 logo,mode = "center"; 842 charge_logo,mode = "center"; 843 connect = <&vp3_out_dsi1>; 844 }; 845 846 route_edp0: route-edp0 { 847 status = "disabled"; 848 logo,uboot = "logo.bmp"; 849 logo,kernel = "logo_kernel.bmp"; 850 logo,mode = "center"; 851 charge_logo,mode = "center"; 852 connect = <&vp2_out_edp0>; 853 }; 854 855 route_edp1: route-edp1 { 856 status = "disabled"; 857 logo,uboot = "logo.bmp"; 858 logo,kernel = "logo_kernel.bmp"; 859 logo,mode = "center"; 860 charge_logo,mode = "center"; 861 }; 862 863 route_hdmi0: route-hdmi0 { 864 status = "disabled"; 865 logo,uboot = "logo.bmp"; 866 logo,kernel = "logo_kernel.bmp"; 867 logo,mode = "center"; 868 charge_logo,mode = "center"; 869 connect = <&vp0_out_hdmi0>; 870 }; 871 872 route_rgb: route-rgb { 873 status = "disabled"; 874 logo,uboot = "logo.bmp"; 875 logo,kernel = "logo_kernel.bmp"; 876 logo,mode = "center"; 877 charge_logo,mode = "center"; 878 connect = <&vp3_out_rgb>; 879 }; 880 }; 881 }; 882 883 dmc: dmc { 884 compatible = "rockchip,rk3588-dmc"; 885 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 886 interrupt-names = "complete"; 887 devfreq-events = <&dfi>; 888 clocks = <&scmi_clk 4>; 889 clock-names = "dmc_clk"; 890 operating-points-v2 = <&dmc_opp_table>; 891 upthreshold = <40>; 892 downdifferential = <20>; 893 system-status-level = < 894 /*system status freq level*/ 895 SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH 896 SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH 897 SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW 898 SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH 899 SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH 900 SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH 901 SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH 902 SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH 903 SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH 904 >; 905 auto-freq-en = <1>; 906 status = "disabled"; 907 }; 908 909 dmc_opp_table: dmc-opp-table { 910 compatible = "operating-points-v2"; 911 912 opp-2750000000 { 913 opp-hz = /bits/ 64 <2750000000>; 914 opp-microvolt = <850000>; 915 }; 916 }; 917 918 firmware { 919 scmi: scmi { 920 compatible = "arm,scmi-smc"; 921 shmem = <&scmi_shmem>; 922 arm,smc-id = <0x82000010>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 926 scmi_clk: protocol@14 { 927 reg = <0x14>; 928 #clock-cells = <1>; 929 930 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, 931 <&scmi_clk SCMI_CLK_CPUB23>; 932 assigned-clock-rates = <1200000000>, 933 <1200000000>; 934 }; 935 936 scmi_reset: protocol@16 { 937 reg = <0x16>; 938 #reset-cells = <1>; 939 }; 940 }; 941 942 sdei: sdei { 943 compatible = "arm,sdei-1.0"; 944 method = "smc"; 945 }; 946 }; 947 948 jpege_ccu: jpege-ccu { 949 compatible = "rockchip,vpu-encoder-v2-ccu"; 950 status = "disabled"; 951 }; 952 953 mpp_srv: mpp-srv { 954 compatible = "rockchip,mpp-service"; 955 rockchip,taskqueue-count = <12>; 956 status = "disabled"; 957 }; 958 959 psci { 960 compatible = "arm,psci-1.0"; 961 method = "smc"; 962 }; 963 964 rkcif_dvp: rkcif-dvp { 965 compatible = "rockchip,rkcif-dvp"; 966 rockchip,hw = <&rkcif>; 967 iommus = <&rkcif_mmu>; 968 status = "disabled"; 969 }; 970 971 rkcif_dvp_sditf: rkcif-dvp-sditf { 972 compatible = "rockchip,rkcif-sditf"; 973 rockchip,cif = <&rkcif_dvp>; 974 status = "disabled"; 975 }; 976 977 rkcif_mipi_lvds: rkcif-mipi-lvds { 978 compatible = "rockchip,rkcif-mipi-lvds"; 979 rockchip,hw = <&rkcif>; 980 iommus = <&rkcif_mmu>; 981 status = "disabled"; 982 }; 983 984 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds_sditf { 985 compatible = "rockchip,rkcif-sditf"; 986 rockchip,cif = <&rkcif_mipi_lvds>; 987 status = "disabled"; 988 }; 989 990 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 991 compatible = "rockchip,rkcif-mipi-lvds"; 992 rockchip,hw = <&rkcif>; 993 iommus = <&rkcif_mmu>; 994 status = "disabled"; 995 }; 996 997 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 998 compatible = "rockchip,rkcif-sditf"; 999 rockchip,cif = <&rkcif_mipi_lvds1>; 1000 status = "disabled"; 1001 }; 1002 1003 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 1004 compatible = "rockchip,rkcif-mipi-lvds"; 1005 rockchip,hw = <&rkcif>; 1006 iommus = <&rkcif_mmu>; 1007 status = "disabled"; 1008 }; 1009 1010 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 1011 compatible = "rockchip,rkcif-sditf"; 1012 rockchip,cif = <&rkcif_mipi_lvds2>; 1013 status = "disabled"; 1014 }; 1015 1016 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 1017 compatible = "rockchip,rkcif-mipi-lvds"; 1018 rockchip,hw = <&rkcif>; 1019 iommus = <&rkcif_mmu>; 1020 status = "disabled"; 1021 }; 1022 1023 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 1024 compatible = "rockchip,rkcif-sditf"; 1025 rockchip,cif = <&rkcif_mipi_lvds3>; 1026 status = "disabled"; 1027 }; 1028 1029 rkisp0_vir0: rkisp0-vir0 { 1030 compatible = "rockchip,rkisp-vir"; 1031 rockchip,hw = <&rkisp0>; 1032 /* 1033 * dual isp process image case 1034 * other rkisp hw and virtual nodes should disabled 1035 * rockchip,hw = <&rkisp_unite>; 1036 */ 1037 status = "disabled"; 1038 }; 1039 1040 rkisp0_vir1: rkisp0-vir1 { 1041 compatible = "rockchip,rkisp-vir"; 1042 rockchip,hw = <&rkisp0>; 1043 status = "disabled"; 1044 }; 1045 1046 rkisp0_vir2: rkisp0-vir2 { 1047 compatible = "rockchip,rkisp-vir"; 1048 rockchip,hw = <&rkisp0>; 1049 status = "disabled"; 1050 }; 1051 1052 rkisp0_vir3: rkisp0-vir3 { 1053 compatible = "rockchip,rkisp-vir"; 1054 rockchip,hw = <&rkisp0>; 1055 status = "disabled"; 1056 }; 1057 1058 rkisp1_vir0: rkisp1-vir0 { 1059 compatible = "rockchip,rkisp-vir"; 1060 rockchip,hw = <&rkisp1>; 1061 status = "disabled"; 1062 }; 1063 1064 rkisp1_vir1: rkisp1-vir1 { 1065 compatible = "rockchip,rkisp-vir"; 1066 rockchip,hw = <&rkisp1>; 1067 status = "disabled"; 1068 }; 1069 1070 rkisp1_vir2: rkisp1-vir2 { 1071 compatible = "rockchip,rkisp-vir"; 1072 rockchip,hw = <&rkisp1>; 1073 status = "disabled"; 1074 }; 1075 1076 rkisp1_vir3: rkisp1-vir3 { 1077 compatible = "rockchip,rkisp-vir"; 1078 rockchip,hw = <&rkisp1>; 1079 status = "disabled"; 1080 }; 1081 1082 rkispp0_vir0: rkispp0-vir0 { 1083 compatible = "rockchip,rk3588-rkispp-vir"; 1084 rockchip,hw = <&rkispp0>; 1085 status = "disabled"; 1086 }; 1087 1088 rkispp1_vir0: rkispp1-vir0 { 1089 compatible = "rockchip,rk3588-rkispp-vir"; 1090 rockchip,hw = <&rkispp1>; 1091 status = "disabled"; 1092 }; 1093 1094 rkvenc_ccu: rkvenc-ccu { 1095 compatible = "rockchip,rkv-encoder-v2-ccu"; 1096 status = "disabled"; 1097 }; 1098 1099 rockchip_suspend: rockchip-suspend { 1100 compatible = "rockchip,pm-rk3588"; 1101 status = "disabled"; 1102 rockchip,sleep-debug-en = <0>; 1103 rockchip,sleep-mode-config = < 1104 (0 1105 | RKPM_SLP_ARMOFF_DDRPD 1106 | RKPM_SLP_PMU_PMUALIVE_32K 1107 | RKPM_SLP_PMU_DIS_OSC 1108 | RKPM_SLP_32K_EXT 1109 | RKPM_SLP_PMU_DBG 1110 ) 1111 >; 1112 rockchip,wakeup-config = < 1113 (0 1114 | RKPM_GPIO_WKUP_EN 1115 ) 1116 >; 1117 }; 1118 1119 rockchip_system_monitor: rockchip-system-monitor { 1120 compatible = "rockchip,system-monitor"; 1121 1122 rockchip,thermal-zone = "soc-thermal"; 1123 }; 1124 1125 thermal_zones: thermal-zones { 1126 soc_thermal: soc-thermal { 1127 polling-delay-passive = <20>; /* milliseconds */ 1128 polling-delay = <1000>; /* milliseconds */ 1129 1130 thermal-sensors = <&tsadc 0>; 1131 trips { 1132 soc_crit: soc-crit { 1133 /* millicelsius */ 1134 temperature = <115000>; 1135 /* millicelsius */ 1136 hysteresis = <2000>; 1137 type = "critical"; 1138 }; 1139 }; 1140 }; 1141 1142 bigcore0_thermal: bigcore0-thermal { 1143 polling-delay-passive = <20>; /* milliseconds */ 1144 polling-delay = <1000>; /* milliseconds */ 1145 thermal-sensors = <&tsadc 1>; 1146 }; 1147 1148 bigcore1_thermal: bigcore1-thermal { 1149 polling-delay-passive = <20>; /* milliseconds */ 1150 polling-delay = <1000>; /* milliseconds */ 1151 thermal-sensors = <&tsadc 2>; 1152 }; 1153 1154 little_core_thermal: littlecore-thermal { 1155 polling-delay-passive = <20>; /* milliseconds */ 1156 polling-delay = <1000>; /* milliseconds */ 1157 thermal-sensors = <&tsadc 3>; 1158 }; 1159 1160 center_thermal: center-thermal { 1161 polling-delay-passive = <20>; /* milliseconds */ 1162 polling-delay = <1000>; /* milliseconds */ 1163 thermal-sensors = <&tsadc 4>; 1164 }; 1165 1166 gpu_thermal: gpu-thermal { 1167 polling-delay-passive = <20>; /* milliseconds */ 1168 polling-delay = <1000>; /* milliseconds */ 1169 thermal-sensors = <&tsadc 5>; 1170 }; 1171 1172 npu_thermal: npu-thermal { 1173 polling-delay-passive = <20>; /* milliseconds */ 1174 polling-delay = <1000>; /* milliseconds */ 1175 thermal-sensors = <&tsadc 6>; 1176 }; 1177 }; 1178 1179 timer { 1180 compatible = "arm,armv8-timer"; 1181 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1182 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1183 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1184 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1185 }; 1186 1187 sram@10f000 { 1188 compatible = "mmio-sram"; 1189 reg = <0x0 0x0010f000 0x0 0x100>; 1190 #address-cells = <1>; 1191 #size-cells = <1>; 1192 ranges = <0 0x0 0x0010f000 0x100>; 1193 1194 scmi_shmem: sram@0 { 1195 compatible = "arm,scmi-shmem"; 1196 reg = <0x0 0x100>; 1197 }; 1198 }; 1199 1200 gpu: gpu@fb000000 { 1201 compatible = "arm,mali-bifrost"; 1202 reg = <0x0 0xfb000000 0x0 0x200000>; 1203 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1206 interrupt-names = "GPU", "MMU", "JOB"; 1207 1208 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 1209 <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>; 1210 clock-names = "clk_mali", "clk_gpu_coregroup", 1211 "clk_gpu_stacks", "clk_gpu"; 1212 power-domains = <&power RK3588_PD_GPU>; 1213 operating-points-v2 = <&gpu_opp_table>; 1214 1215 upthreshold = <30>; 1216 downdifferential = <10>; 1217 1218 status = "disabled"; 1219 }; 1220 1221 gpu_opp_table: gpu-opp-table { 1222 compatible = "operating-points-v2"; 1223 1224 clocks = <&cru CLK_GPU>; 1225 clock-names = "clk"; 1226 rockchip,grf = <&gpu_grf>; 1227 volt-mem-read-margin = < 1228 855000 1 1229 765000 2 1230 675000 3 1231 585000 4 1232 >; 1233 1234 opp-198000000 { 1235 opp-hz = /bits/ 64 <198000000>; 1236 opp-microvolt = <675000 675000 850000>, 1237 <675000 675000 850000>; 1238 }; 1239 opp-297000000 { 1240 opp-hz = /bits/ 64 <297000000>; 1241 opp-microvolt = <675000 675000 850000>, 1242 <675000 675000 850000>; 1243 }; 1244 opp-396000000 { 1245 opp-hz = /bits/ 64 <396000000>; 1246 opp-microvolt = <675000 675000 850000>, 1247 <675000 675000 850000>; 1248 }; 1249 opp-500000000 { 1250 opp-hz = /bits/ 64 <500000000>; 1251 opp-microvolt = <675000 675000 850000>, 1252 <675000 675000 850000>; 1253 }; 1254 opp-600000000 { 1255 opp-hz = /bits/ 64 <600000000>; 1256 opp-microvolt = <675000 675000 850000>, 1257 <675000 675000 850000>; 1258 }; 1259 opp-700000000 { 1260 opp-hz = /bits/ 64 <700000000>; 1261 opp-microvolt = <700000 700000 850000>, 1262 <700000 700000 850000>; 1263 }; 1264 opp-800000000 { 1265 opp-hz = /bits/ 64 <800000000>; 1266 opp-microvolt = <750000 750000 850000>, 1267 <750000 750000 850000>; 1268 }; 1269 opp-900000000 { 1270 opp-hz = /bits/ 64 <900000000>; 1271 opp-microvolt = <800000 800000 850000>, 1272 <800000 800000 850000>; 1273 }; 1274 opp-1000000000 { 1275 opp-hz = /bits/ 64 <1000000000>; 1276 opp-microvolt = <850000 850000 850000>, 1277 <850000 850000 850000>; 1278 }; 1279 }; 1280 1281 usbdrd3_0: usbdrd3_0 { 1282 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 1283 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 1284 <&cru ACLK_USB3OTG0>; 1285 clock-names = "ref", "suspend", "bus"; 1286 #address-cells = <2>; 1287 #size-cells = <2>; 1288 ranges; 1289 status = "disabled"; 1290 1291 usbdrd_dwc3_0: usb@fc000000 { 1292 compatible = "snps,dwc3"; 1293 reg = <0x0 0xfc000000 0x0 0x400000>; 1294 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&power RK3588_PD_USB>; 1296 resets = <&cru SRST_A_USB3OTG0>; 1297 reset-names = "usb3-otg"; 1298 dr_mode = "otg"; 1299 phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; 1300 phy-names = "usb2-phy", "usb3-phy"; 1301 phy_type = "utmi_wide"; 1302 snps,dis_enblslpm_quirk; 1303 snps,dis-u1-entry-quirk; 1304 snps,dis-u2-entry-quirk; 1305 snps,dis-u2-freeclk-exists-quirk; 1306 snps,dis-del-phy-power-chg-quirk; 1307 snps,dis-tx-ipgap-linecheck-quirk; 1308 quirk-skip-phy-init; 1309 status = "disabled"; 1310 }; 1311 }; 1312 1313 usb_host0_ehci: usb@fc800000 { 1314 compatible = "generic-ehci"; 1315 reg = <0x0 0xfc800000 0x0 0x40000>; 1316 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>; 1318 clock-names = "usbhost", "arbiter", "utmi"; 1319 phys = <&u2phy2_host>; 1320 phy-names = "usb2-phy"; 1321 power-domains = <&power RK3588_PD_USB>; 1322 status = "disabled"; 1323 }; 1324 1325 usb_host0_ohci: usb@fc840000 { 1326 compatible = "generic-ohci"; 1327 reg = <0x0 0xfc840000 0x0 0x40000>; 1328 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>; 1330 clock-names = "usbhost", "arbiter", "utmi"; 1331 phys = <&u2phy2_host>; 1332 phy-names = "usb2-phy"; 1333 power-domains = <&power RK3588_PD_USB>; 1334 status = "disabled"; 1335 }; 1336 1337 usb_host1_ehci: usb@fc880000 { 1338 compatible = "generic-ehci"; 1339 reg = <0x0 0xfc880000 0x0 0x40000>; 1340 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>; 1342 clock-names = "usbhost", "arbiter", "utmi"; 1343 phys = <&u2phy3_host>; 1344 phy-names = "usb2-phy"; 1345 power-domains = <&power RK3588_PD_USB>; 1346 status = "disabled"; 1347 }; 1348 1349 usb_host1_ohci: usb@fc8c0000 { 1350 compatible = "generic-ohci"; 1351 reg = <0x0 0xfc8c0000 0x0 0x40000>; 1352 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>; 1354 clock-names = "usbhost", "arbiter", "utmi"; 1355 phys = <&u2phy3_host>; 1356 phy-names = "usb2-phy"; 1357 power-domains = <&power RK3588_PD_USB>; 1358 status = "disabled"; 1359 }; 1360 1361 mmu600_pcie: iommu@fc900000 { 1362 compatible = "arm,smmu-v3"; 1363 reg = <0x0 0xfc900000 0x0 0x200000>; 1364 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1368 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1369 #iommu-cells = <1>; 1370 status = "disabled"; 1371 }; 1372 1373 mmu600_php: iommu@fcb00000 { 1374 compatible = "arm,smmu-v3"; 1375 reg = <0x0 0xfcb00000 0x0 0x200000>; 1376 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1380 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1381 #iommu-cells = <1>; 1382 status = "disabled"; 1383 }; 1384 1385 usbhost3_0: usbhost3_0 { 1386 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 1387 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 1388 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 1389 <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>; 1390 clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; 1391 #address-cells = <2>; 1392 #size-cells = <2>; 1393 ranges; 1394 status = "disabled"; 1395 1396 usbhost_dwc3_0: usb@fcd00000 { 1397 compatible = "snps,dwc3"; 1398 reg = <0x0 0xfcd00000 0x0 0x400000>; 1399 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1400 resets = <&cru SRST_A_USB3OTG2>; 1401 reset-names = "usb3-host"; 1402 dr_mode = "host"; 1403 phys = <&combphy2_psu PHY_TYPE_USB3>; 1404 phy-names = "usb3-phy"; 1405 phy_type = "utmi_wide"; 1406 snps,dis_enblslpm_quirk; 1407 snps,dis-u2-freeclk-exists-quirk; 1408 snps,dis-del-phy-power-chg-quirk; 1409 snps,dis-tx-ipgap-linecheck-quirk; 1410 snps,dis_rxdet_inp3_quirk; 1411 status = "disabled"; 1412 }; 1413 }; 1414 1415 pmu0_grf: syscon@fd588000 { 1416 compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; 1417 reg = <0x0 0xfd588000 0x0 0x2000>; 1418 1419 reboot_mode: reboot-mode { 1420 compatible = "syscon-reboot-mode"; 1421 offset = <0x80>; 1422 mode-bootloader = <BOOT_BL_DOWNLOAD>; 1423 mode-charge = <BOOT_CHARGING>; 1424 mode-fastboot = <BOOT_FASTBOOT>; 1425 mode-loader = <BOOT_BL_DOWNLOAD>; 1426 mode-normal = <BOOT_NORMAL>; 1427 mode-recovery = <BOOT_RECOVERY>; 1428 mode-ums = <BOOT_UMS>; 1429 mode-panic = <BOOT_PANIC>; 1430 mode-watchdog = <BOOT_WATCHDOG>; 1431 }; 1432 }; 1433 1434 pmu1_grf: syscon@fd58a000 { 1435 compatible = "rockchip,rk3588-pmu1-grf", "syscon"; 1436 reg = <0x0 0xfd58a000 0x0 0x2000>; 1437 }; 1438 1439 sys_grf: syscon@fd58c000 { 1440 compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd"; 1441 reg = <0x0 0xfd58c000 0x0 0x1000>; 1442 1443 rgb: rgb { 1444 compatible = "rockchip,rk3588-rgb"; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&bt1120_pins>; 1447 status = "disabled"; 1448 1449 ports { 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 port@0 { 1454 reg = <0>; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 1458 rgb_in_vp3: endpoint@2 { 1459 reg = <2>; 1460 remote-endpoint = <&vp3_out_rgb>; 1461 status = "disabled"; 1462 }; 1463 }; 1464 }; 1465 }; 1466 }; 1467 1468 bigcore0_grf: syscon@fd590000 { 1469 compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; 1470 reg = <0x0 0xfd590000 0x0 0x100>; 1471 }; 1472 1473 bigcore1_grf: syscon@fd592000 { 1474 compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; 1475 reg = <0x0 0xfd592000 0x0 0x100>; 1476 }; 1477 1478 gpu_grf: syscon@fd5a0000 { 1479 compatible = "rockchip,rk3588-gpu-grf", "syscon"; 1480 reg = <0x0 0xfd5a0000 0x0 0x100>; 1481 }; 1482 1483 npu_grf: syscon@fd5a2000 { 1484 compatible = "rockchip,rk3588-npu-grf", "syscon"; 1485 reg = <0x0 0xfd5a2000 0x0 0x100>; 1486 }; 1487 1488 vop_grf: syscon@fd5a4000 { 1489 compatible = "rockchip,rk3588-vop-grf", "syscon"; 1490 reg = <0x0 0xfd5a4000 0x0 0x2000>; 1491 }; 1492 1493 vo0_grf: syscon@fd5a6000 { 1494 compatible = "rockchip,rk3588-vo-grf", "syscon"; 1495 reg = <0x0 0xfd5a6000 0x0 0x2000>; 1496 }; 1497 1498 vo1_grf: syscon@fd5a8000 { 1499 compatible = "rockchip,rk3588-vo-grf", "syscon"; 1500 reg = <0x0 0xfd5a8000 0x0 0x100>; 1501 }; 1502 1503 usb_grf: syscon@fd5ac000 { 1504 compatible = "rockchip,rk3588-usb-grf", "syscon"; 1505 reg = <0x0 0xfd5ac000 0x0 0x4000>; 1506 }; 1507 1508 php_grf: syscon@fd5b0000 { 1509 compatible = "rockchip,rk3588-php-grf", "syscon"; 1510 reg = <0x0 0xfd5b0000 0x0 0x1000>; 1511 }; 1512 1513 mipidphy0_grf: syscon@fd5b4000 { 1514 compatible = "rockchip,mipi-dphy-grf", "syscon"; 1515 reg = <0x0 0xfd5b4000 0x0 0x1000>; 1516 }; 1517 1518 mipidphy1_grf: syscon@fd5b5000 { 1519 compatible = "rockchip,mipi-dphy-grf", "syscon"; 1520 reg = <0x0 0xfd5b5000 0x0 0x1000>; 1521 }; 1522 1523 pipe_phy0_grf: syscon@fd5bc000 { 1524 compatible = "rockchip,pipe-phy-grf", "syscon"; 1525 reg = <0x0 0xfd5bc000 0x0 0x100>; 1526 }; 1527 1528 pipe_phy2_grf: syscon@fd5c4000 { 1529 compatible = "rockchip,pipe-phy-grf", "syscon"; 1530 reg = <0x0 0xfd5c4000 0x0 0x100>; 1531 }; 1532 1533 usbdpphy0_grf: syscon@fd5c8000 { 1534 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 1535 reg = <0x0 0xfd5c8000 0x0 0x4000>; 1536 }; 1537 1538 usb2phy0_grf: syscon@fd5d0000 { 1539 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 1540 "simple-mfd"; 1541 reg = <0x0 0xfd5d0000 0x0 0x4000>; 1542 #address-cells = <1>; 1543 #size-cells = <1>; 1544 1545 u2phy0: usb2-phy@0 { 1546 compatible = "rockchip,rk3588-usb2phy"; 1547 reg = <0x0 0x10>; 1548 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 1549 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 1550 reset-names = "phy", "apb"; 1551 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 1552 clock-names = "phyclk"; 1553 clock-output-names = "usb480m_phy0"; 1554 #clock-cells = <0>; 1555 rockchip,usbctrl-grf = <&usb_grf>; 1556 status = "disabled"; 1557 1558 u2phy0_otg: otg-port { 1559 #phy-cells = <0>; 1560 status = "disabled"; 1561 }; 1562 }; 1563 }; 1564 1565 usb2phy2_grf: syscon@fd5d8000 { 1566 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 1567 "simple-mfd"; 1568 reg = <0x0 0xfd5d8000 0x0 0x4000>; 1569 #address-cells = <1>; 1570 #size-cells = <1>; 1571 1572 u2phy2: usb2-phy@8000 { 1573 compatible = "rockchip,rk3588-usb2phy"; 1574 reg = <0x8000 0x10>; 1575 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 1576 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 1577 reset-names = "phy", "apb"; 1578 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 1579 clock-names = "phyclk"; 1580 clock-output-names = "usb480m_phy2"; 1581 #clock-cells = <0>; 1582 status = "disabled"; 1583 1584 u2phy2_host: host-port { 1585 #phy-cells = <0>; 1586 status = "disabled"; 1587 }; 1588 }; 1589 }; 1590 1591 usb2phy3_grf: syscon@fd5dc000 { 1592 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 1593 "simple-mfd"; 1594 reg = <0x0 0xfd5dc000 0x0 0x4000>; 1595 #address-cells = <1>; 1596 #size-cells = <1>; 1597 1598 u2phy3: usb2-phy@c000 { 1599 compatible = "rockchip,rk3588-usb2phy"; 1600 reg = <0xc000 0x10>; 1601 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1602 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 1603 reset-names = "phy", "apb"; 1604 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 1605 clock-names = "phyclk"; 1606 clock-output-names = "usb480m_phy3"; 1607 #clock-cells = <0>; 1608 status = "disabled"; 1609 1610 u2phy3_host: host-port { 1611 #phy-cells = <0>; 1612 status = "disabled"; 1613 }; 1614 }; 1615 }; 1616 1617 hdptxphy0_grf: syscon@fd5e0000 { 1618 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 1619 reg = <0x0 0xfd5e0000 0x0 0x100>; 1620 }; 1621 1622 mipidcphy0_grf: syscon@fd5e8000 { 1623 compatible = "rockchip,mipi-dcphy-grf", "syscon"; 1624 reg = <0x0 0xfd5e8000 0x0 0x4000>; 1625 }; 1626 1627 mipidcphy1_grf: syscon@fd5ec000 { 1628 compatible = "rockchip,mipi-dcphy-grf", "syscon"; 1629 reg = <0x0 0xfd5ec000 0x0 0x4000>; 1630 }; 1631 1632 ioc: syscon@fd5f0000 { 1633 compatible = "rockchip,rk3588-ioc", "syscon"; 1634 reg = <0x0 0xfd5f0000 0x0 0x10000>; 1635 }; 1636 1637 syssram: sram@fd600000 { 1638 compatible = "mmio-sram"; 1639 reg = <0x0 0xfd600000 0x0 0x100000>; 1640 1641 #address-cells = <1>; 1642 #size-cells = <1>; 1643 ranges = <0x0 0x0 0xfd600000 0x100000>; 1644 /* start address and size should be 4k algin */ 1645 rkvdec0_sram: rkvdec-sram@0 { 1646 reg = <0 0x80000>; 1647 }; 1648 rkvdec1_sram: rkvdec-sram@80000 { 1649 reg = <0x80000 0x80000>; 1650 }; 1651 }; 1652 1653 cru: clock-controller@fd7c0000 { 1654 compatible = "rockchip,rk3588-cru"; 1655 rockchip,grf = <&php_grf>; 1656 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 1657 #clock-cells = <1>; 1658 #reset-cells = <1>; 1659 1660 assigned-clocks = 1661 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 1662 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 1663 <&cru ARMCLK_L>, 1664 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, 1665 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 1666 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 1667 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 1668 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 1669 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 1670 <&cru CLK_GPU>; 1671 assigned-clock-rates = 1672 <100000000>, <786432000>, 1673 <850000000>, <1188000000>, 1674 <816000000>, 1675 <702000000>, <200000000>, 1676 <400000000>, <500000000>, 1677 <800000000>, <100000000>, 1678 <400000000>, <100000000>, 1679 <200000000>, <500000000>, 1680 <375000000>, <150000000>, 1681 <200000000>; 1682 }; 1683 1684 i2c0: i2c@fd880000 { 1685 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1686 reg = <0x0 0xfd880000 0x0 0x1000>; 1687 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1688 clock-names = "i2c", "pclk"; 1689 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1690 pinctrl-names = "default"; 1691 pinctrl-0 = <&i2c0m0_xfer>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 uart0: serial@fd890000 { 1698 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1699 reg = <0x0 0xfd890000 0x0 0x100>; 1700 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1701 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1702 clock-names = "baudclk", "apb_pclk"; 1703 reg-shift = <2>; 1704 reg-io-width = <4>; 1705 dmas = <&dmac0 6>, <&dmac0 7>; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&uart0m1_xfer>; 1708 status = "disabled"; 1709 }; 1710 1711 pwm0: pwm@fd8b0000 { 1712 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1713 reg = <0x0 0xfd8b0000 0x0 0x10>; 1714 #pwm-cells = <3>; 1715 pinctrl-names = "active"; 1716 pinctrl-0 = <&pwm0m0_pins>; 1717 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1718 clock-names = "pwm", "pclk"; 1719 status = "disabled"; 1720 }; 1721 1722 pwm1: pwm@fd8b0010 { 1723 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1724 reg = <0x0 0xfd8b0010 0x0 0x10>; 1725 #pwm-cells = <3>; 1726 pinctrl-names = "active"; 1727 pinctrl-0 = <&pwm1m0_pins>; 1728 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1729 clock-names = "pwm", "pclk"; 1730 status = "disabled"; 1731 }; 1732 1733 pwm2: pwm@fd8b0020 { 1734 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1735 reg = <0x0 0xfd8b0020 0x0 0x10>; 1736 #pwm-cells = <3>; 1737 pinctrl-names = "active"; 1738 pinctrl-0 = <&pwm2m0_pins>; 1739 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1740 clock-names = "pwm", "pclk"; 1741 status = "disabled"; 1742 }; 1743 1744 pwm3: pwm@fd8b0030 { 1745 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1746 reg = <0x0 0xfd8b0030 0x0 0x10>; 1747 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1749 #pwm-cells = <3>; 1750 pinctrl-names = "active"; 1751 pinctrl-0 = <&pwm3m0_pins>; 1752 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 1753 clock-names = "pwm", "pclk"; 1754 status = "disabled"; 1755 }; 1756 1757 pmu: power-management@fd8d8000 { 1758 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 1759 reg = <0x0 0xfd8d8000 0x0 0x400>; 1760 1761 power: power-controller { 1762 compatible = "rockchip,rk3588-power-controller"; 1763 #power-domain-cells = <1>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 status = "okay"; 1767 1768 /* These power domains are grouped by VD_NPU */ 1769 power-domain@RK3588_PD_NPU { 1770 reg = <RK3588_PD_NPU>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 power-domain@RK3588_PD_NPUTOP { 1775 reg = <RK3588_PD_NPUTOP>; 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 clocks = <&cru HCLK_NPU_ROOT>, 1779 <&cru PCLK_NPU_ROOT>, 1780 <&cru CLK_NPU_DSU0>, 1781 <&cru HCLK_NPU_CM0_ROOT>; 1782 pm_qos = <&qos_npu0_mwr>, 1783 <&qos_npu0_mro>, 1784 <&qos_mcu_npu>; 1785 1786 power-domain@RK3588_PD_NPU1 { 1787 reg = <RK3588_PD_NPU1>; 1788 clocks = <&cru HCLK_NPU_ROOT>, 1789 <&cru PCLK_NPU_ROOT>, 1790 <&cru CLK_NPU_DSU0>; 1791 pm_qos = <&qos_npu1>; 1792 }; 1793 power-domain@RK3588_PD_NPU2 { 1794 reg = <RK3588_PD_NPU2>; 1795 clocks = <&cru HCLK_NPU_ROOT>, 1796 <&cru PCLK_NPU_ROOT>, 1797 <&cru CLK_NPU_DSU0>; 1798 pm_qos = <&qos_npu2>; 1799 }; 1800 }; 1801 }; 1802 /* These power domains are grouped by VD_GPU */ 1803 power-domain@RK3588_PD_GPU { 1804 reg = <RK3588_PD_GPU>; 1805 clocks = <&cru CLK_GPU>, 1806 <&cru CLK_GPU_COREGROUP>, 1807 <&cru CLK_GPU_STACKS>; 1808 pm_qos = <&qos_gpu_m0>, 1809 <&qos_gpu_m1>, 1810 <&qos_gpu_m2>, 1811 <&qos_gpu_m3>; 1812 }; 1813 /* These power domains are grouped by VD_VCODEC */ 1814 power-domain@RK3588_PD_VCODEC { 1815 reg = <RK3588_PD_VCODEC>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 1819 power-domain@RK3588_PD_RKVDEC0 { 1820 reg = <RK3588_PD_RKVDEC0>; 1821 clocks = <&cru HCLK_RKVDEC0>, 1822 <&cru HCLK_VDPU_ROOT>, 1823 <&cru ACLK_VDPU_ROOT>, 1824 <&cru ACLK_RKVDEC0>, 1825 <&cru ACLK_RKVDEC_CCU>; 1826 pm_qos = <&qos_rkvdec0>; 1827 }; 1828 power-domain@RK3588_PD_RKVDEC1 { 1829 reg = <RK3588_PD_RKVDEC1>; 1830 clocks = <&cru HCLK_RKVDEC1>, 1831 <&cru HCLK_VDPU_ROOT>, 1832 <&cru ACLK_VDPU_ROOT>, 1833 <&cru ACLK_RKVDEC1>; 1834 pm_qos = <&qos_rkvdec1>; 1835 }; 1836 power-domain@RK3588_PD_VENC0 { 1837 reg = <RK3588_PD_VENC0>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 clocks = <&cru HCLK_RKVENC0>, 1841 <&cru ACLK_RKVENC0>; 1842 pm_qos = <&qos_rkvenc0_m0ro>, 1843 <&qos_rkvenc0_m1ro>, 1844 <&qos_rkvenc0_m2wo>; 1845 1846 power-domain@RK3588_PD_VENC1 { 1847 reg = <RK3588_PD_VENC1>; 1848 clocks = <&cru HCLK_RKVENC1>, 1849 <&cru HCLK_RKVENC0>, 1850 <&cru ACLK_RKVENC0>, 1851 <&cru ACLK_RKVENC1>; 1852 pm_qos = <&qos_rkvenc1_m0ro>, 1853 <&qos_rkvenc1_m1ro>, 1854 <&qos_rkvenc1_m2wo>; 1855 }; 1856 }; 1857 }; 1858 /* These power domains are grouped by VD_LOGIC */ 1859 power-domain@RK3588_PD_VDPU { 1860 reg = <RK3588_PD_VDPU>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 clocks = <&cru HCLK_VDPU_ROOT>, 1864 <&cru ACLK_VDPU_LOW_ROOT>, 1865 <&cru ACLK_VDPU_ROOT>, 1866 <&cru ACLK_JPEG_DECODER_ROOT>, 1867 <&cru ACLK_IEP2P0>, 1868 <&cru HCLK_IEP2P0>, 1869 <&cru ACLK_JPEG_ENCODER0>, 1870 <&cru HCLK_JPEG_ENCODER0>, 1871 <&cru ACLK_JPEG_ENCODER1>, 1872 <&cru HCLK_JPEG_ENCODER1>, 1873 <&cru ACLK_JPEG_ENCODER2>, 1874 <&cru HCLK_JPEG_ENCODER2>, 1875 <&cru ACLK_JPEG_ENCODER3>, 1876 <&cru HCLK_JPEG_ENCODER3>, 1877 <&cru ACLK_JPEG_DECODER>, 1878 <&cru HCLK_JPEG_DECODER>, 1879 <&cru ACLK_RGA2>, 1880 <&cru HCLK_RGA2>; 1881 pm_qos = <&qos_iep>, 1882 <&qos_jpeg_dec>, 1883 <&qos_jpeg_enc0>, 1884 <&qos_jpeg_enc1>, 1885 <&qos_jpeg_enc2>, 1886 <&qos_jpeg_enc3>, 1887 <&qos_rga2_mro>, 1888 <&qos_rga2_mwo>; 1889 1890 power-domain@RK3588_PD_AV1 { 1891 reg = <RK3588_PD_AV1>; 1892 clocks = <&cru PCLK_AV1>, 1893 <&cru ACLK_AV1>, 1894 <&cru HCLK_VDPU_ROOT>; 1895 pm_qos = <&qos_av1>; 1896 }; 1897 power-domain@RK3588_PD_RKVDEC0 { 1898 reg = <RK3588_PD_RKVDEC0>; 1899 clocks = <&cru HCLK_RKVDEC0>, 1900 <&cru HCLK_VDPU_ROOT>, 1901 <&cru ACLK_VDPU_ROOT>, 1902 <&cru ACLK_RKVDEC0>; 1903 pm_qos = <&qos_rkvdec0>; 1904 }; 1905 power-domain@RK3588_PD_RKVDEC1 { 1906 reg = <RK3588_PD_RKVDEC1>; 1907 clocks = <&cru HCLK_RKVDEC1>, 1908 <&cru HCLK_VDPU_ROOT>, 1909 <&cru ACLK_VDPU_ROOT>; 1910 pm_qos = <&qos_rkvdec1>; 1911 }; 1912 power-domain@RK3588_PD_RGA30 { 1913 reg = <RK3588_PD_RGA30>; 1914 clocks = <&cru ACLK_RGA3_0>, 1915 <&cru HCLK_RGA3_0>; 1916 pm_qos = <&qos_rga3_0>; 1917 }; 1918 }; 1919 power-domain@RK3588_PD_VOP { 1920 reg = <RK3588_PD_VOP>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 clocks = <&cru PCLK_VOP_ROOT>, 1924 <&cru HCLK_VOP_ROOT>, 1925 <&cru ACLK_VOP>; 1926 pm_qos = <&qos_vop_m0>, 1927 <&qos_vop_m1>; 1928 1929 power-domain@RK3588_PD_VO0 { 1930 reg = <RK3588_PD_VO0>; 1931 clocks = <&cru PCLK_VO0_ROOT>, 1932 <&cru PCLK_VO0_S_ROOT>, 1933 <&cru HCLK_VO0_S_ROOT>, 1934 <&cru ACLK_VO0_ROOT>, 1935 <&cru HCLK_HDCP0>, 1936 <&cru ACLK_HDCP0>, 1937 <&cru HCLK_VOP_ROOT>; 1938 pm_qos = <&qos_hdcp0>; 1939 }; 1940 }; 1941 power-domain@RK3588_PD_VO1 { 1942 reg = <RK3588_PD_VO1>; 1943 clocks = <&cru PCLK_VO1_ROOT>, 1944 <&cru PCLK_VO1_S_ROOT>, 1945 <&cru HCLK_VO1_S_ROOT>, 1946 <&cru HCLK_HDCP1>, 1947 <&cru ACLK_HDCP1>, 1948 <&cru ACLK_HDMIRX_ROOT>, 1949 <&cru HCLK_VO1USB_TOP_ROOT>; 1950 pm_qos = <&qos_hdcp1>, 1951 <&qos_hdmirx>; 1952 }; 1953 power-domain@RK3588_PD_VI { 1954 reg = <RK3588_PD_VI>; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 clocks = <&cru HCLK_VI_ROOT>, 1958 <&cru PCLK_VI_ROOT>, 1959 <&cru HCLK_ISP0>, 1960 <&cru ACLK_ISP0>, 1961 <&cru HCLK_VICAP>, 1962 <&cru ACLK_VICAP>; 1963 pm_qos = <&qos_isp0_mro>, 1964 <&qos_isp0_mwo>, 1965 <&qos_vicap_m0>, 1966 <&qos_vicap_m1>; 1967 1968 power-domain@RK3588_PD_ISP1 { 1969 reg = <RK3588_PD_ISP1>; 1970 clocks = <&cru HCLK_ISP1>, 1971 <&cru ACLK_ISP1>, 1972 <&cru HCLK_VI_ROOT>, 1973 <&cru PCLK_VI_ROOT>; 1974 pm_qos = <&qos_isp1_mwo>, 1975 <&qos_isp1_mro>; 1976 }; 1977 power-domain@RK3588_PD_FEC { 1978 reg = <RK3588_PD_FEC>; 1979 clocks = <&cru HCLK_FISHEYE0>, 1980 <&cru ACLK_FISHEYE0>, 1981 <&cru HCLK_FISHEYE1>, 1982 <&cru ACLK_FISHEYE1>, 1983 <&cru PCLK_VI_ROOT>; 1984 pm_qos = <&qos_fisheye0>, 1985 <&qos_fisheye1>; 1986 }; 1987 }; 1988 power-domain@RK3588_PD_RGA31 { 1989 reg = <RK3588_PD_RGA31>; 1990 clocks = <&cru HCLK_RGA3_1>, 1991 <&cru ACLK_RGA3_1>; 1992 pm_qos = <&qos_rga3_1>; 1993 }; 1994 power-domain@RK3588_PD_USB { 1995 reg = <RK3588_PD_USB>; 1996 clocks = <&cru PCLK_PHP_ROOT>, 1997 <&cru ACLK_USB_ROOT>, 1998 <&cru HCLK_USB_ROOT>, 1999 <&cru HCLK_HOST0>, 2000 <&cru HCLK_HOST_ARB0>, 2001 <&cru HCLK_HOST1>, 2002 <&cru HCLK_HOST_ARB1>; 2003 pm_qos = <&qos_usb3_0>, 2004 <&qos_usb3_1>, 2005 <&qos_usb2host_0>, 2006 <&qos_usb2host_1>; 2007 }; 2008 power-domain@RK3588_PD_GMAC { 2009 reg = <RK3588_PD_GMAC>; 2010 clocks = <&cru PCLK_PHP_ROOT>, 2011 <&cru ACLK_PCIE_ROOT>, 2012 <&cru ACLK_PHP_ROOT>; 2013 }; 2014 power-domain@RK3588_PD_PCIE { 2015 reg = <RK3588_PD_PCIE>; 2016 clocks = <&cru PCLK_PHP_ROOT>, 2017 <&cru ACLK_PCIE_ROOT>, 2018 <&cru ACLK_PHP_ROOT>; 2019 }; 2020 power-domain@RK3588_PD_SDIO { 2021 reg = <RK3588_PD_SDIO>; 2022 clocks = <&cru HCLK_SDIO>, 2023 <&cru HCLK_NVM_ROOT>; 2024 pm_qos = <&qos_sdio>; 2025 }; 2026 power-domain@RK3588_PD_AUDIO { 2027 reg = <RK3588_PD_AUDIO>; 2028 clocks = <&cru HCLK_AUDIO_ROOT>, 2029 <&cru PCLK_AUDIO_ROOT>; 2030 }; 2031 power-domain@RK3588_PD_SDMMC { 2032 reg = <RK3588_PD_SDMMC>; 2033 pm_qos = <&qos_sdmmc>; 2034 }; 2035 }; 2036 }; 2037 2038 pvtm@fda40000 { 2039 compatible = "rockchip,rk3588-bigcore0-pvtm"; 2040 reg = <0x0 0xfda40000 0x0 0x100>; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 pvtm@0 { 2044 reg = <0>; 2045 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 2046 clock-names = "clk", "pclk"; 2047 }; 2048 }; 2049 2050 pvtm@fda50000 { 2051 compatible = "rockchip,rk3588-bigcore1-pvtm"; 2052 reg = <0x0 0xfda50000 0x0 0x100>; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 pvtm@1 { 2056 reg = <1>; 2057 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 2058 clock-names = "clk", "pclk"; 2059 }; 2060 }; 2061 2062 pvtm@fda60000 { 2063 compatible = "rockchip,rk3588-litcore-pvtm"; 2064 reg = <0x0 0xfda60000 0x0 0x100>; 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 pvtm@2 { 2068 reg = <2>; 2069 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 2070 clock-names = "clk", "pclk"; 2071 }; 2072 }; 2073 2074 pvtm@fdaf0000 { 2075 compatible = "rockchip,rk3588-npu-pvtm"; 2076 reg = <0x0 0xfdaf0000 0x0 0x100>; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 pvtm@3 { 2080 reg = <3>; 2081 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 2082 clock-names = "clk", "pclk"; 2083 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 2084 reset-names = "rts", "rst-p"; 2085 }; 2086 }; 2087 2088 pvtm@fdb30000 { 2089 compatible = "rockchip,rk3588-gpu-pvtm"; 2090 reg = <0x0 0xfdb30000 0x0 0x100>; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 pvtm@4 { 2094 reg = <4>; 2095 clocks = <&cru CLK_GPU_PVTM>; 2096 clock-names = "clk"; 2097 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 2098 reset-names = "rts", "rst-p"; 2099 }; 2100 }; 2101 2102 rknpu: npu@fdab0000 { 2103 compatible = "rockchip,rk3588-rknpu"; 2104 reg = <0x0 0xfdab0000 0x0 0x10000>, 2105 <0x0 0xfdac0000 0x0 0x10000>, 2106 <0x0 0xfdad0000 0x0 0x10000>; 2107 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2110 interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; 2111 clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>, 2112 <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, 2113 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, 2114 <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>; 2115 clock-names = "clk_npu", "aclk0", 2116 "aclk1", "aclk2", 2117 "hclk0", "hclk1", 2118 "hclk2", "pclk"; 2119 assigned-clocks = <&cru CLK_NPU_DSU0>; 2120 assigned-clock-rates = <200000000>; 2121 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>, 2122 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>; 2123 reset-names = "srst_a0", "srst_a1", "srst_a2", 2124 "srst_h0", "srst_h1", "srst_h2"; 2125 power-domains = <&power RK3588_PD_NPUTOP>, 2126 <&power RK3588_PD_NPU1>, 2127 <&power RK3588_PD_NPU2>; 2128 power-domain-names = "npu0", "npu1", "npu2"; 2129 operating-points-v2 = <&npu_opp_table>; 2130 iommus = <&rknpu_mmu>; 2131 status = "disabled"; 2132 }; 2133 2134 npu_opp_table: npu-opp-table { 2135 compatible = "operating-points-v2"; 2136 2137 clocks = <&cru PCLK_NPU_GRF>; 2138 clock-names = "pclk"; 2139 rockchip,grf = <&npu_grf>; 2140 volt-mem-read-margin = < 2141 855000 1 2142 765000 2 2143 675000 3 2144 585000 4 2145 >; 2146 2147 rockchip,init-freq = <1000000>; /* KHz */ 2148 2149 opp-198000000 { 2150 opp-hz = /bits/ 64 <198000000>; 2151 opp-microvolt = <675000 675000 850000>, 2152 <750000 750000 850000>; 2153 }; 2154 opp-297000000 { 2155 opp-hz = /bits/ 64 <297000000>; 2156 opp-microvolt = <675000 675000 850000>, 2157 <750000 750000 850000>; 2158 }; 2159 opp-396000000 { 2160 opp-hz = /bits/ 64 <396000000>; 2161 opp-microvolt = <675000 675000 850000>, 2162 <675000 675000 850000>; 2163 }; 2164 opp-500000000 { 2165 opp-hz = /bits/ 64 <500000000>; 2166 opp-microvolt = <675000 675000 850000>, 2167 <675000 675000 850000>; 2168 }; 2169 opp-600000000 { 2170 opp-hz = /bits/ 64 <600000000>; 2171 opp-microvolt = <675000 675000 850000>, 2172 <675000 675000 850000>; 2173 }; 2174 opp-700000000 { 2175 opp-hz = /bits/ 64 <700000000>; 2176 opp-microvolt = <700000 700000 850000>, 2177 <700000 700000 850000>; 2178 }; 2179 opp-800000000 { 2180 opp-hz = /bits/ 64 <800000000>; 2181 opp-microvolt = <750000 750000 850000>, 2182 <750000 750000 850000>; 2183 }; 2184 opp-900000000 { 2185 opp-hz = /bits/ 64 <900000000>; 2186 opp-microvolt = <800000 800000 850000>, 2187 <800000 800000 850000>; 2188 }; 2189 opp-1000000000 { 2190 opp-hz = /bits/ 64 <1000000000>; 2191 opp-microvolt = <850000 850000 850000>, 2192 <850000 850000 850000>; 2193 }; 2194 }; 2195 2196 rknpu_mmu: iommu@fdab9000 { 2197 compatible = "rockchip,iommu-v2"; 2198 reg = <0x0 0xfdab9000 0x0 0x100>, 2199 <0x0 0xfdaba000 0x0 0x100>, 2200 <0x0 0xfdaca000 0x0 0x100>, 2201 <0x0 0xfdada000 0x0 0x100>; 2202 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2205 interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu"; 2206 clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, 2207 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>; 2208 clock-names = "aclk0", "aclk1", "aclk2", 2209 "iface0", "iface1", "iface2"; 2210 #iommu-cells = <0>; 2211 status = "disabled"; 2212 }; 2213 2214 vdpu: vdpu@fdb50400 { 2215 compatible = "rockchip,vpu-decoder-v2"; 2216 reg = <0x0 0xfdb50400 0x0 0x400>; 2217 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2218 interrupt-names = "irq_vdpu"; 2219 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 2220 clock-names = "aclk_vcodec", "hclk_vcodec"; 2221 rockchip,normal-rates = <594000000>, <0>; 2222 assigned-clocks = <&cru ACLK_VPU>; 2223 assigned-clock-rates = <594000000>; 2224 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 2225 reset-names = "video_a", "video_h"; 2226 rockchip,skip-pmu-idle-request; 2227 iommus = <&vdpu_mmu>; 2228 rockchip,srv = <&mpp_srv>; 2229 rockchip,taskqueue-node = <0>; 2230 power-domains = <&power RK3588_PD_VDPU>; 2231 status = "disabled"; 2232 }; 2233 2234 vdpu_mmu: iommu@fdb50800 { 2235 compatible = "rockchip,iommu-v2"; 2236 reg = <0x0 0xfdb50800 0x0 0x40>; 2237 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2238 interrupt-names = "irq_vdpu_mmu"; 2239 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 2240 clock-names = "aclk", "iface"; 2241 power-domains = <&power RK3588_PD_VDPU>; 2242 #iommu-cells = <0>; 2243 status = "disabled"; 2244 }; 2245 2246 rga3_core0: rga@fdb60000 { 2247 compatible = "rockchip,rga3_core0"; 2248 reg = <0x0 0xfdb60000 0x0 0x1000>; 2249 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2250 interrupt-names = "rga3_core0_irq"; 2251 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; 2252 clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0"; 2253 power-domains = <&power RK3588_PD_RGA30>; 2254 iommus = <&rga3_0_mmu>; 2255 status = "disabled"; 2256 }; 2257 2258 rga3_0_mmu: iommu@fdb60f00 { 2259 compatible = "rockchip,iommu-v2"; 2260 reg = <0x0 0xfdb60f00 0x0 0x100>; 2261 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2262 interrupt-names = "rga3_0_mmu"; 2263 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 2264 clock-names = "aclk", "iface"; 2265 power-domains = <&power RK3588_PD_RGA30>; 2266 #iommu-cells = <0>; 2267 status = "disabled"; 2268 }; 2269 2270 rga3_core1: rga@fdb70000 { 2271 compatible = "rockchip,rga3_core1"; 2272 reg = <0x0 0xfdb70000 0x0 0x1000>; 2273 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2274 interrupt-names = "rga3_core1_irq"; 2275 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; 2276 clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1"; 2277 power-domains = <&power RK3588_PD_RGA31>; 2278 iommus = <&rga3_1_mmu>; 2279 status = "disabled"; 2280 }; 2281 2282 rga3_1_mmu: iommu@fdb70f00 { 2283 compatible = "rockchip,iommu-v2"; 2284 reg = <0x0 0xfdb70f00 0x0 0x100>; 2285 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2286 interrupt-names = "rga3_1_mmu"; 2287 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 2288 clock-names = "aclk", "iface"; 2289 power-domains = <&power RK3588_PD_RGA31>; 2290 #iommu-cells = <0>; 2291 status = "disabled"; 2292 }; 2293 2294 rga2: rga@fdb80000 { 2295 compatible = "rockchip,rga2_core0"; 2296 reg = <0x0 0xfdb80000 0x0 0x1000>; 2297 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2298 interrupt-names = "rga2_irq"; 2299 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 2300 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 2301 power-domains = <&power RK3588_PD_VDPU>; 2302 status = "disabled"; 2303 }; 2304 2305 jpegd: jpegd@fdb90000 { 2306 compatible = "rockchip,rkv-jpeg-decoder-v1"; 2307 reg = <0x0 0xfdb90000 0x0 0x400>; 2308 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 2309 interrupt-names = "irq_jpegd"; 2310 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 2311 clock-names = "aclk_vcodec", "hclk_vcodec"; 2312 rockchip,normal-rates = <600000000>, <0>; 2313 assigned-clocks = <&cru ACLK_JPEG_DECODER>; 2314 assigned-clock-rates = <600000000>; 2315 resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>; 2316 reset-names = "video_a", "video_h"; 2317 rockchip,skip-pmu-idle-request; 2318 iommus = <&jpegd_mmu>; 2319 rockchip,srv = <&mpp_srv>; 2320 rockchip,taskqueue-node = <1>; 2321 power-domains = <&power RK3588_PD_VDPU>; 2322 status = "disabled"; 2323 }; 2324 2325 jpegd_mmu: iommu@fdb90480 { 2326 compatible = "rockchip,iommu-v2"; 2327 reg = <0x0 0xfdb90480 0x0 0x40>; 2328 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 2329 interrupt-names = "irq_jpegd_mmu"; 2330 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 2331 clock-names = "aclk", "iface"; 2332 power-domains = <&power RK3588_PD_VDPU>; 2333 #iommu-cells = <0>; 2334 status = "disabled"; 2335 }; 2336 2337 jpege0: jpege-core@fdba0000 { 2338 compatible = "rockchip,vpu-encoder-v2-core"; 2339 reg = <0x0 0xfdba0000 0x0 0x400>; 2340 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 2341 interrupt-names = "irq_jpege0"; 2342 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 2343 clock-names = "aclk_vcodec", "hclk_vcodec"; 2344 rockchip,normal-rates = <594000000>, <0>; 2345 assigned-clocks = <&cru ACLK_JPEG_ENCODER0>; 2346 assigned-clock-rates = <594000000>; 2347 resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>; 2348 reset-names = "video_a", "video_h"; 2349 rockchip,skip-pmu-idle-request; 2350 iommus = <&jpege0_mmu>; 2351 rockchip,srv = <&mpp_srv>; 2352 rockchip,taskqueue-node = <2>; 2353 rockchip,ccu = <&jpege_ccu>; 2354 power-domains = <&power RK3588_PD_VDPU>; 2355 status = "disabled"; 2356 }; 2357 2358 jpege0_mmu: iommu@fdba0800 { 2359 compatible = "rockchip,iommu-v2"; 2360 reg = <0x0 0xfdba0800 0x0 0x40>; 2361 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 2362 interrupt-names = "irq_jpege0_mmu"; 2363 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 2364 clock-names = "aclk", "iface"; 2365 power-domains = <&power RK3588_PD_VDPU>; 2366 #iommu-cells = <0>; 2367 status = "disabled"; 2368 }; 2369 2370 jpege1: jpege-core@fdba4000 { 2371 compatible = "rockchip,vpu-encoder-v2-core"; 2372 reg = <0x0 0xfdba4000 0x0 0x400>; 2373 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2374 interrupt-names = "irq_jpege1"; 2375 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 2376 clock-names = "aclk_vcodec", "hclk_vcodec"; 2377 rockchip,normal-rates = <594000000>, <0>; 2378 assigned-clocks = <&cru ACLK_JPEG_ENCODER1>; 2379 assigned-clock-rates = <594000000>; 2380 resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>; 2381 reset-names = "video_a", "video_h"; 2382 rockchip,skip-pmu-idle-request; 2383 iommus = <&jpege1_mmu>; 2384 rockchip,srv = <&mpp_srv>; 2385 rockchip,taskqueue-node = <3>; 2386 rockchip,ccu = <&jpege_ccu>; 2387 power-domains = <&power RK3588_PD_VDPU>; 2388 status = "disabled"; 2389 }; 2390 2391 jpege1_mmu: iommu@fdba4800 { 2392 compatible = "rockchip,iommu-v2"; 2393 reg = <0x0 0xfdba4800 0x0 0x40>; 2394 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2395 interrupt-names = "irq_jpege1_mmu"; 2396 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 2397 clock-names = "aclk", "iface"; 2398 power-domains = <&power RK3588_PD_VDPU>; 2399 #iommu-cells = <0>; 2400 status = "disabled"; 2401 }; 2402 2403 jpege2: jpege-core@fdba8000 { 2404 compatible = "rockchip,vpu-encoder-v2-core"; 2405 reg = <0x0 0xfdba8000 0x0 0x400>; 2406 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 2407 interrupt-names = "irq_jpege2"; 2408 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 2409 clock-names = "aclk_vcodec", "hclk_vcodec"; 2410 rockchip,normal-rates = <594000000>, <0>; 2411 assigned-clocks = <&cru ACLK_JPEG_ENCODER2>; 2412 assigned-clock-rates = <594000000>; 2413 resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>; 2414 reset-names = "video_a", "video_h"; 2415 rockchip,skip-pmu-idle-request; 2416 iommus = <&jpege2_mmu>; 2417 rockchip,srv = <&mpp_srv>; 2418 rockchip,taskqueue-node = <4>; 2419 rockchip,ccu = <&jpege_ccu>; 2420 power-domains = <&power RK3588_PD_VDPU>; 2421 status = "disabled"; 2422 }; 2423 2424 jpege2_mmu: iommu@fdba8800 { 2425 compatible = "rockchip,iommu-v2"; 2426 reg = <0x0 0xfdba8800 0x0 0x40>; 2427 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2428 interrupt-names = "irq_jpege2_mmu"; 2429 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 2430 clock-names = "aclk", "iface"; 2431 power-domains = <&power RK3588_PD_VDPU>; 2432 #iommu-cells = <0>; 2433 status = "disabled"; 2434 }; 2435 2436 jpege3: jpege-core@fdbac000 { 2437 compatible = "rockchip,vpu-encoder-v2-core"; 2438 reg = <0x0 0xfdbac000 0x0 0x400>; 2439 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2440 interrupt-names = "irq_jpege3"; 2441 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 2442 clock-names = "aclk_vcodec", "hclk_vcodec"; 2443 rockchip,normal-rates = <594000000>, <0>; 2444 assigned-clocks = <&cru ACLK_JPEG_ENCODER3>; 2445 assigned-clock-rates = <594000000>; 2446 resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>; 2447 reset-names = "video_a", "video_h"; 2448 rockchip,skip-pmu-idle-request; 2449 iommus = <&jpege3_mmu>; 2450 rockchip,srv = <&mpp_srv>; 2451 rockchip,taskqueue-node = <5>; 2452 rockchip,ccu = <&jpege_ccu>; 2453 power-domains = <&power RK3588_PD_VDPU>; 2454 status = "disabled"; 2455 }; 2456 2457 jpege3_mmu: iommu@fdbac800 { 2458 compatible = "rockchip,iommu-v2"; 2459 reg = <0x0 0xfdbac800 0x0 0x40>; 2460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 2461 interrupt-names = "irq_jpege3_mmu"; 2462 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 2463 clock-names = "aclk", "iface"; 2464 power-domains = <&power RK3588_PD_VDPU>; 2465 #iommu-cells = <0>; 2466 status = "disabled"; 2467 }; 2468 2469 iep: iep@fdbb0000 { 2470 compatible = "rockchip,iep-v2"; 2471 reg = <0x0 0xfdbb0000 0x0 0x500>; 2472 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2473 interrupt-names = "irq_iep"; 2474 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>; 2475 clock-names = "aclk", "hclk", "sclk"; 2476 resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>; 2477 reset-names = "rst_a", "rst_h", "rst_s"; 2478 rockchip,skip-pmu-idle-request; 2479 power-domains = <&power RK3588_PD_VDPU>; 2480 rockchip,srv = <&mpp_srv>; 2481 rockchip,taskqueue-node = <6>; 2482 iommus = <&iep_mmu>; 2483 status = "disabled"; 2484 }; 2485 2486 iep_mmu: iommu@fdbb0800 { 2487 compatible = "rockchip,iommu-v2"; 2488 reg = <0x0 0xfdbb0800 0x0 0x100>; 2489 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2490 interrupt-names = "irq_iep_mmu"; 2491 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 2492 clock-names = "aclk", "iface"; 2493 #iommu-cells = <0>; 2494 power-domains = <&power RK3588_PD_VDPU>; 2495 status = "disabled"; 2496 }; 2497 2498 rkvenc0: rkvenc-core@fdbd0000 { 2499 compatible = "rockchip,rkv-encoder-v2-core"; 2500 reg = <0x0 0xfdbd0000 0x0 0x6000>; 2501 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2502 interrupt-names = "irq_rkvenc0"; 2503 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; 2504 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 2505 rockchip,normal-rates = <600000000>, <0>, <800000000>; 2506 assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; 2507 assigned-clock-rates = <600000000>, <800000000>; 2508 resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>; 2509 reset-names = "video_a", "video_h", "video_core"; 2510 rockchip,skip-pmu-idle-request; 2511 iommus = <&rkvenc0_mmu>; 2512 rockchip,srv = <&mpp_srv>; 2513 rockchip,ccu = <&rkvenc_ccu>; 2514 rockchip,taskqueue-node = <7>; 2515 rockchip,task-capacity = <8>; 2516 power-domains = <&power RK3588_PD_VENC0>; 2517 status = "disabled"; 2518 }; 2519 2520 rkvenc0_mmu: iommu@fdbdf000 { 2521 compatible = "rockchip,iommu-v2"; 2522 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 2523 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2525 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 2526 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 2527 clock-names = "aclk", "iface"; 2528 rockchip,disable-mmu-reset; 2529 rockchip,enable-cmd-retry; 2530 rockchip,shootdown-entire; 2531 #iommu-cells = <0>; 2532 power-domains = <&power RK3588_PD_VENC0>; 2533 status = "disabled"; 2534 }; 2535 2536 rkvenc1: rkvenc-core@fdbe0000 { 2537 compatible = "rockchip,rkv-encoder-v2-core"; 2538 reg = <0x0 0xfdbe0000 0x0 0x6000>; 2539 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2540 interrupt-names = "irq_rkvenc1"; 2541 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; 2542 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 2543 rockchip,normal-rates = <600000000>, <0>, <800000000>; 2544 assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; 2545 assigned-clock-rates = <600000000>, <800000000>; 2546 resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>; 2547 reset-names = "video_a", "video_h", "video_core"; 2548 rockchip,skip-pmu-idle-request; 2549 iommus = <&rkvenc1_mmu>; 2550 rockchip,srv = <&mpp_srv>; 2551 rockchip,ccu = <&rkvenc_ccu>; 2552 rockchip,taskqueue-node = <7>; 2553 rockchip,task-capacity = <8>; 2554 power-domains = <&power RK3588_PD_VENC1>; 2555 status = "disabled"; 2556 }; 2557 2558 rkvenc1_mmu: iommu@fdbef000 { 2559 compatible = "rockchip,iommu-v2"; 2560 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 2561 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2563 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 2564 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 2565 lock-names = "aclk", "iface"; 2566 rockchip,disable-mmu-reset; 2567 rockchip,enable-cmd-retry; 2568 rockchip,shootdown-entire; 2569 #iommu-cells = <0>; 2570 power-domains = <&power RK3588_PD_VENC1>; 2571 status = "disabled"; 2572 }; 2573 2574 rkvdec_ccu: rkvdec-ccu@fdc30000 { 2575 compatible = "rockchip,rkv-decoder-v2-ccu"; 2576 reg = <0x0 0xfdc30000 0x0 0x100>; 2577 reg-names = "ccu"; 2578 clocks = <&cru ACLK_RKVDEC_CCU>; 2579 clock-names = "aclk_ccu"; 2580 assigned-clocks = <&cru ACLK_RKVDEC_CCU>; 2581 assigned-clock-rates = <600000000>; 2582 resets = <&cru SRST_A_RKVDEC_CCU>; 2583 reset-names = "video_ccu"; 2584 rockchip,skip-pmu-idle-request; 2585 power-domains = <&power RK3588_PD_RKVDEC0>; 2586 status = "disabled"; 2587 }; 2588 2589 rkvdec0: rkvdec-core@fdc38000 { 2590 compatible = "rockchip,rkv-decoder-v2"; 2591 reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>; 2592 reg-names = "regs", "link"; 2593 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2594 interrupt-names = "irq_rkvdec0"; 2595 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, 2596 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; 2597 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", 2598 "clk_cabac", "clk_hevc_cabac"; 2599 rockchip,normal-rates = <800000000>, <0>, <600000000>, 2600 <600000000>, <1000000000>; 2601 assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, 2602 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; 2603 assigned-clock-rates = <800000000>, <600000000>, 2604 <600000000>, <1000000000>; 2605 resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>, 2606 <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>; 2607 reset-names = "video_a", "video_h", "video_core", 2608 "video_cabac", "video_hevc_cabac"; 2609 rockchip,skip-pmu-idle-request; 2610 iommus = <&rkvdec0_mmu>; 2611 rockchip,srv = <&mpp_srv>; 2612 rockchip,ccu = <&rkvdec_ccu>; 2613 rockchip,core-mask = <0x00010001>; 2614 rockchip,taskqueue-node = <9>; 2615 rockchip,sram = <&rkvdec0_sram>; 2616 /* rcb_iova: start and size */ 2617 rockchip,rcb-iova = <0x10000000 0x100000>; 2618 rockchip,rcb-min-width = <512>; 2619 power-domains = <&power RK3588_PD_RKVDEC0>; 2620 status = "disabled"; 2621 }; 2622 2623 rkvdec0_mmu: iommu@fdc38700 { 2624 compatible = "rockchip,iommu-v2"; 2625 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 2626 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2627 interrupt-names = "irq_rkvdec0_mmu"; 2628 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 2629 clock-names = "aclk", "iface"; 2630 rockchip,disable-mmu-reset; 2631 rockchip,enable-cmd-retry; 2632 rockchip,shootdown-entire; 2633 #iommu-cells = <0>; 2634 power-domains = <&power RK3588_PD_RKVDEC0>; 2635 status = "disabled"; 2636 }; 2637 2638 rkvdec1: rkvdec-core@fdc48000 { 2639 compatible = "rockchip,rkv-decoder-v2"; 2640 reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>; 2641 reg-names = "regs", "link"; 2642 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2643 interrupt-names = "irq_rkvdec1"; 2644 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, 2645 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; 2646 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", 2647 "clk_cabac", "clk_hevc_cabac"; 2648 rockchip,normal-rates = <800000000>, <0>, <600000000>, 2649 <600000000>, <1000000000>; 2650 assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, 2651 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; 2652 assigned-clock-rates = <800000000>, <600000000>, 2653 <600000000>, <1000000000>; 2654 resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>, 2655 <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>; 2656 reset-names = "video_a", "video_h", "video_core", 2657 "video_cabac", "video_hevc_cabac"; 2658 rockchip,skip-pmu-idle-request; 2659 iommus = <&rkvdec1_mmu>; 2660 rockchip,srv = <&mpp_srv>; 2661 rockchip,ccu = <&rkvdec_ccu>; 2662 rockchip,core-mask = <0x00020002>; 2663 rockchip,taskqueue-node = <9>; 2664 rockchip,sram = <&rkvdec1_sram>; 2665 /* rcb_iova: start and size */ 2666 rockchip,rcb-iova = <0x10100000 0x100000>; 2667 rockchip,rcb-min-width = <512>; 2668 power-domains = <&power RK3588_PD_RKVDEC1>; 2669 status = "disabled"; 2670 }; 2671 2672 rkvdec1_mmu: iommu@fdc48700 { 2673 compatible = "rockchip,iommu-v2"; 2674 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 2675 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2676 interrupt-names = "irq_rkvdec1_mmu"; 2677 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 2678 clock-names = "aclk", "iface"; 2679 rockchip,disable-mmu-reset; 2680 rockchip,enable-cmd-retry; 2681 rockchip,shootdown-entire; 2682 #iommu-cells = <0>; 2683 power-domains = <&power RK3588_PD_RKVDEC1>; 2684 status = "disabled"; 2685 }; 2686 2687 rkisp_unite: rkisp-unite@fdcb0000 { 2688 compatible = "rockchip,rk3588-rkisp-unite"; 2689 reg = <0x0 0xfdcb0000 0x0 0x10000>, 2690 <0x0 0xfdcc0000 0x0 0x10000>; 2691 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2694 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 2695 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 2696 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, 2697 <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>, 2698 <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>, 2699 <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>; 2700 clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", 2701 "clk_isp_core_marvin0", "clk_isp_core_vicap0", 2702 "aclk_isp1", "hclk_isp1", "clk_isp_core1", 2703 "clk_isp_core_marvin1", "clk_isp_core_vicap1"; 2704 power-domains = <&power RK3588_PD_ISP1>; 2705 iommus = <&rkisp_unite_mmu>; 2706 status = "disabled"; 2707 }; 2708 2709 rkisp0: rkisp@fdcb0000 { 2710 compatible = "rockchip,rk3588-rkisp"; 2711 reg = <0x0 0xfdcb0000 0x0 0x7f00>; 2712 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2715 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 2716 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 2717 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, 2718 <&cru CLK_ISP0_CORE_VICAP>; 2719 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", 2720 "clk_isp_core_marvin", "clk_isp_core_vicap"; 2721 power-domains = <&power RK3588_PD_VI>; 2722 iommus = <&isp0_mmu>; 2723 status = "disabled"; 2724 }; 2725 2726 rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 { 2727 compatible = "rockchip,iommu-v2"; 2728 reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>; 2729 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2731 interrupt-names = "isp0_mmu", "isp1_mmu"; 2732 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 2733 <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 2734 clock-names = "aclk0", "iface0", "aclk1", "iface1"; 2735 power-domains = <&power RK3588_PD_ISP1>; 2736 #iommu-cells = <0>; 2737 rockchip,disable-mmu-reset; 2738 status = "disabled"; 2739 }; 2740 2741 isp0_mmu: iommu@fdcb7f00 { 2742 compatible = "rockchip,iommu-v2"; 2743 reg = <0x0 0xfdcb7f00 0x0 0x100>; 2744 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 2745 interrupt-names = "isp0_mmu"; 2746 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 2747 clock-names = "aclk", "iface"; 2748 power-domains = <&power RK3588_PD_VI>; 2749 #iommu-cells = <0>; 2750 rockchip,disable-mmu-reset; 2751 status = "disabled"; 2752 }; 2753 2754 rkisp1: rkisp@fdcc0000 { 2755 compatible = "rockchip,rk3588-rkisp"; 2756 reg = <0x0 0xfdcc0000 0x0 0x7f00>; 2757 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2760 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 2761 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, 2762 <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>, 2763 <&cru CLK_ISP1_CORE_VICAP>; 2764 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", 2765 "clk_isp_core_marvin", "clk_isp_core_vicap"; 2766 power-domains = <&power RK3588_PD_ISP1>; 2767 iommus = <&isp1_mmu>; 2768 status = "disabled"; 2769 }; 2770 2771 isp1_mmu: iommu@fdcc7f00 { 2772 compatible = "rockchip,iommu-v2"; 2773 reg = <0x0 0xfdcc7f00 0x0 0x100>; 2774 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2775 interrupt-names = "isp1_mmu"; 2776 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 2777 clock-names = "aclk", "iface"; 2778 power-domains = <&power RK3588_PD_ISP1>; 2779 #iommu-cells = <0>; 2780 rockchip,disable-mmu-reset; 2781 status = "disabled"; 2782 }; 2783 2784 rkispp0: rkispp@fdcd0000 { 2785 compatible = "rockchip,rk3588-rkispp"; 2786 reg = <0x0 0xfdcd0000 0x0 0x0f00>; 2787 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 2788 interrupt-names = "fec_irq"; 2789 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, 2790 <&cru CLK_FISHEYE0_CORE>; 2791 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 2792 power-domains = <&power RK3588_PD_FEC>; 2793 iommus = <&fec0_mmu>; 2794 status = "disabled"; 2795 }; 2796 2797 fec0_mmu: iommu@fdcd0f00 { 2798 compatible = "rockchip,iommu-v2"; 2799 reg = <0x0 0xfdcd0f00 0x0 0x100>; 2800 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2801 interrupt-names = "fec0_mmu"; 2802 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>; 2803 clock-names = "aclk", "iface", "pclk"; 2804 power-domains = <&power RK3588_PD_FEC>; 2805 #iommu-cells = <0>; 2806 rockchip,disable-mmu-reset; 2807 status = "disabled"; 2808 }; 2809 2810 rkispp1: rkispp@fdcd8000 { 2811 compatible = "rockchip,rk3588-rkispp"; 2812 reg = <0x0 0xfdcd8000 0x0 0x0f00>; 2813 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2814 interrupt-names = "fec_irq"; 2815 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, 2816 <&cru CLK_FISHEYE1_CORE>; 2817 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 2818 power-domains = <&power RK3588_PD_FEC>; 2819 iommus = <&fec1_mmu>; 2820 status = "disabled"; 2821 }; 2822 2823 fec1_mmu: iommu@fdcd8f00 { 2824 compatible = "rockchip,iommu-v2"; 2825 reg = <0x0 0xfdcd8f00 0x0 0x100>; 2826 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 2827 interrupt-names = "fec1_mmu"; 2828 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>; 2829 clock-names = "aclk", "iface", "pclk"; 2830 power-domains = <&power RK3588_PD_FEC>; 2831 #iommu-cells = <0>; 2832 rockchip,disable-mmu-reset; 2833 status = "disabled"; 2834 }; 2835 2836 rkcif: rkcif@fdce0000 { 2837 compatible = "rockchip,rk3588-cif"; 2838 reg = <0x0 0xfdce0000 0x0 0x800>; 2839 reg-names = "cif_regs"; 2840 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2841 interrupt-names = "cif-intr"; 2842 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>; 2843 clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; 2844 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>; 2845 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d"; 2846 assigned-clocks = <&cru DCLK_VICAP>; 2847 assigned-clock-rates = <600000000>; 2848 power-domains = <&power RK3588_PD_VI>; 2849 rockchip,grf = <&sys_grf>; 2850 iommus = <&rkcif_mmu>; 2851 status = "disabled"; 2852 }; 2853 2854 rkcif_mmu: iommu@fdce0800 { 2855 compatible = "rockchip,iommu-v2"; 2856 reg = <0x0 0xfdce0800 0x0 0x100>, 2857 <0x0 0xfdce0900 0x0 0x100>; 2858 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2859 interrupt-names = "cif_mmu"; 2860 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 2861 clock-names = "aclk", "iface"; 2862 power-domains = <&power RK3588_PD_VI>; 2863 rockchip,disable-mmu-reset; 2864 #iommu-cells = <0>; 2865 status = "disabled"; 2866 }; 2867 2868 mipi0_csi2: mipi0-csi2@fdd10000 { 2869 compatible = "rockchip,rk3588-mipi-csi2"; 2870 reg = <0x0 0xfdd10000 0x0 0x10000>; 2871 reg-names = "csihost_regs"; 2872 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2873 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2874 interrupt-names = "csi-intr1", "csi-intr2"; 2875 clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>; 2876 clock-names = "pclk_csi2host", "iclk_csi2host"; 2877 resets = <&cru SRST_P_CSI_HOST_0>, <&cru SRST_CSIHOST0_VICAP>; 2878 reset-names = "srst_csihost_p", "srst_csihost_vicap"; 2879 status = "disabled"; 2880 }; 2881 2882 mipi1_csi2: mipi1-csi2@fdd20000 { 2883 compatible = "rockchip,rk3588-mipi-csi2"; 2884 reg = <0x0 0xfdd20000 0x0 0x10000>; 2885 reg-names = "csihost_regs"; 2886 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2888 interrupt-names = "csi-intr1", "csi-intr2"; 2889 clocks = <&cru PCLK_CSI_HOST_1>, <&cru ICLK_CSIHOST1>; 2890 clock-names = "pclk_csi2host", "iclk_csi2host"; 2891 resets = <&cru SRST_P_CSI_HOST_1>, <&cru SRST_CSIHOST1_VICAP>; 2892 reset-names = "srst_csihost_p", "srst_csihost_vicap"; 2893 status = "disabled"; 2894 }; 2895 2896 mipi2_csi2: mipi2-csi2@fdd30000 { 2897 compatible = "rockchip,rk3588-mipi-csi2"; 2898 reg = <0x0 0xfdd30000 0x0 0x10000>; 2899 reg-names = "csihost_regs"; 2900 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2902 interrupt-names = "csi-intr1", "csi-intr2"; 2903 clocks = <&cru PCLK_CSI_HOST_2>; 2904 clock-names = "pclk_csi2host"; 2905 resets = <&cru SRST_P_CSI_HOST_2>, <&cru SRST_CSIHOST2_VICAP>; 2906 reset-names = "srst_csihost_p", "srst_csihost_vicap"; 2907 status = "disabled"; 2908 }; 2909 2910 mipi3_csi2: mipi3-csi2@fdd40000 { 2911 compatible = "rockchip,rk3588-mipi-csi2"; 2912 reg = <0x0 0xfdd40000 0x0 0x10000>; 2913 reg-names = "csihost_regs"; 2914 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2916 interrupt-names = "csi-intr1", "csi-intr2"; 2917 clocks = <&cru PCLK_CSI_HOST_3>; 2918 clock-names = "pclk_csi2host"; 2919 resets = <&cru SRST_P_CSI_HOST_3>, <&cru SRST_CSIHOST3_VICAP>; 2920 reset-names = "srst_csihost_p", "srst_csihost_vicap"; 2921 status = "disabled"; 2922 }; 2923 2924 vop: vop@fdd90000 { 2925 compatible = "rockchip,rk3588-vop"; 2926 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 2927 reg-names = "regs", "gamma_lut"; 2928 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2929 clocks = <&cru ACLK_VOP>, 2930 <&cru HCLK_VOP>, 2931 <&cru DCLK_VOP0>, 2932 <&cru DCLK_VOP1>, 2933 <&cru DCLK_VOP2>, 2934 <&cru DCLK_VOP3>, 2935 <&cru PCLK_VOP_ROOT>, 2936 <&cru DCLK_VOP0_SRC>, 2937 <&cru DCLK_VOP1_SRC>, 2938 <&cru DCLK_VOP2_SRC>, 2939 <&hdptxphy_hdmi0>; 2940 clock-names = "aclk_vop", 2941 "hclk_vop", 2942 "dclk_vp0", 2943 "dclk_vp1", 2944 "dclk_vp2", 2945 "dclk_vp3", 2946 "pclk_vop", 2947 "dclk_src_vp0", 2948 "dclk_src_vp1", 2949 "dclk_src_vp2", 2950 "hdmi0_phy_pll"; 2951 resets = <&cru SRST_A_VOP>, 2952 <&cru SRST_H_VOP>, 2953 <&cru SRST_D_VOP0>, 2954 <&cru SRST_D_VOP1>, 2955 <&cru SRST_D_VOP2>, 2956 <&cru SRST_D_VOP3>; 2957 reset-names = "axi", 2958 "ahb", 2959 "dclk_vp0", 2960 "dclk_vp1", 2961 "dclk_vp2", 2962 "dclk_vp3"; 2963 iommus = <&vop_mmu>; 2964 power-domains = <&power RK3588_PD_VOP>; 2965 rockchip,grf = <&sys_grf>; 2966 rockchip,vop-grf = <&vop_grf>; 2967 rockchip,vo1-grf = <&vo1_grf>; 2968 rockchip,pmu = <&pmu>; 2969 2970 status = "disabled"; 2971 2972 vop_out: ports { 2973 #address-cells = <1>; 2974 #size-cells = <0>; 2975 2976 vp0: port@0 { 2977 #address-cells = <1>; 2978 #size-cells = <0>; 2979 reg = <0>; 2980 2981 vp0_out_dp0: endpoint@0 { 2982 reg = <0>; 2983 remote-endpoint = <&dp0_in_vp0>; 2984 }; 2985 2986 vp0_out_edp0: endpoint@1 { 2987 reg = <1>; 2988 remote-endpoint = <&edp0_in_vp0>; 2989 }; 2990 2991 vp0_out_hdmi0: endpoint@2 { 2992 reg = <2>; 2993 remote-endpoint = <&hdmi0_in_vp0>; 2994 }; 2995 }; 2996 2997 vp1: port@1 { 2998 #address-cells = <1>; 2999 #size-cells = <0>; 3000 reg = <1>; 3001 3002 vp1_out_dp0: endpoint@0 { 3003 reg = <0>; 3004 remote-endpoint = <&dp0_in_vp1>; 3005 }; 3006 3007 vp1_out_edp0: endpoint@1 { 3008 reg = <1>; 3009 remote-endpoint = <&edp0_in_vp1>; 3010 }; 3011 3012 vp1_out_hdmi0: endpoint@2 { 3013 reg = <2>; 3014 remote-endpoint = <&hdmi0_in_vp1>; 3015 }; 3016 }; 3017 3018 vp2: port@2 { 3019 #address-cells = <1>; 3020 #size-cells = <0>; 3021 reg = <2>; 3022 3023 assigned-clocks = <&cru DCLK_VOP2_SRC>; 3024 assigned-clock-parents = <&cru PLL_V0PLL>; 3025 3026 vp2_out_dp0: endpoint@0 { 3027 reg = <0>; 3028 remote-endpoint = <&dp0_in_vp2>; 3029 }; 3030 3031 vp2_out_edp0: endpoint@1 { 3032 reg = <1>; 3033 remote-endpoint = <&edp0_in_vp2>; 3034 }; 3035 3036 vp2_out_hdmi0: endpoint@2 { 3037 reg = <2>; 3038 remote-endpoint = <&hdmi0_in_vp2>; 3039 }; 3040 3041 vp2_out_dsi0: endpoint@3 { 3042 reg = <3>; 3043 remote-endpoint = <&dsi0_in_vp2>; 3044 }; 3045 3046 vp2_out_dsi1: endpoint@4 { 3047 reg = <4>; 3048 remote-endpoint = <&dsi1_in_vp2>; 3049 }; 3050 }; 3051 3052 vp3: port@3 { 3053 #address-cells = <1>; 3054 #size-cells = <0>; 3055 reg = <3>; 3056 3057 vp3_out_dsi0: endpoint@0 { 3058 reg = <0>; 3059 remote-endpoint = <&dsi0_in_vp3>; 3060 }; 3061 3062 vp3_out_dsi1: endpoint@1 { 3063 reg = <1>; 3064 remote-endpoint = <&dsi1_in_vp3>; 3065 }; 3066 3067 vp3_out_rgb: endpoint@2 { 3068 reg = <2>; 3069 remote-endpoint = <&rgb_in_vp3>; 3070 }; 3071 }; 3072 }; 3073 }; 3074 3075 vop_mmu: iommu@fdd97e00 { 3076 compatible = "rockchip,iommu-v2"; 3077 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 3078 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3079 interrupt-names = "vop_mmu"; 3080 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 3081 clock-names = "aclk", "iface"; 3082 #iommu-cells = <0>; 3083 rockchip,disable-device-link-resume; 3084 rockchip,shootdown-entire; 3085 status = "disabled"; 3086 }; 3087 3088 spdif_tx2: spdif-tx@fddb0000 { 3089 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 3090 reg = <0x0 0xfddb0000 0x0 0x1000>; 3091 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 3092 dmas = <&dmac1 6>; 3093 dma-names = "tx"; 3094 clock-names = "mclk", "hclk"; 3095 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; 3096 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 3097 assigned-clock-parents = <&cru PLL_AUPLL>; 3098 power-domains = <&power RK3588_PD_VO0>; 3099 #sound-dai-cells = <0>; 3100 status = "disabled"; 3101 }; 3102 3103 i2s4_8ch: i2s@fddc0000 { 3104 compatible = "rockchip,rk3588-i2s-tdm"; 3105 reg = <0x0 0xfddc0000 0x0 0x1000>; 3106 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 3107 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 3108 clock-names = "mclk_tx", "mclk_rx", "hclk"; 3109 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 3110 assigned-clock-parents = <&cru PLL_AUPLL>; 3111 dmas = <&dmac2 0>; 3112 dma-names = "tx"; 3113 power-domains = <&power RK3588_PD_VO0>; 3114 resets = <&cru SRST_M_I2S4_8CH_TX>; 3115 reset-names = "tx-m"; 3116 rockchip,playback-only; 3117 #sound-dai-cells = <0>; 3118 status = "disabled"; 3119 }; 3120 3121 spdif_tx3: spdif-tx@fdde0000 { 3122 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 3123 reg = <0x0 0xfdde0000 0x0 0x1000>; 3124 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 3125 dmas = <&dmac1 7>; 3126 dma-names = "tx"; 3127 clock-names = "mclk", "hclk"; 3128 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 3129 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 3130 assigned-clock-parents = <&cru PLL_AUPLL>; 3131 power-domains = <&power RK3588_PD_VO1>; 3132 #sound-dai-cells = <0>; 3133 status = "disabled"; 3134 }; 3135 3136 i2s5_8ch: i2s@fddf0000 { 3137 compatible = "rockchip,rk3588-i2s-tdm"; 3138 reg = <0x0 0xfddf0000 0x0 0x1000>; 3139 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 3140 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 3141 clock-names = "mclk_tx", "mclk_rx", "hclk"; 3142 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 3143 assigned-clock-parents = <&cru PLL_AUPLL>; 3144 dmas = <&dmac2 2>; 3145 dma-names = "tx"; 3146 power-domains = <&power RK3588_PD_VO1>; 3147 resets = <&cru SRST_M_I2S5_8CH_TX>; 3148 reset-names = "tx-m"; 3149 rockchip,playback-only; 3150 #sound-dai-cells = <0>; 3151 status = "disabled"; 3152 }; 3153 3154 i2s9_8ch: i2s@fddfc000 { 3155 compatible = "rockchip,rk3588-i2s-tdm"; 3156 reg = <0x0 0xfddfc000 0x0 0x1000>; 3157 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 3158 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 3159 clock-names = "mclk_tx", "mclk_rx", "hclk"; 3160 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 3161 assigned-clock-parents = <&cru PLL_AUPLL>; 3162 dmas = <&dmac2 23>; 3163 dma-names = "rx"; 3164 power-domains = <&power RK3588_PD_VO1>; 3165 resets = <&cru SRST_M_I2S9_8CH_RX>; 3166 reset-names = "rx-m"; 3167 rockchip,capture-only; 3168 #sound-dai-cells = <0>; 3169 status = "disabled"; 3170 }; 3171 3172 spdif_rx0: spdif-rx@fde08000 { 3173 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 3174 reg = <0x0 0xfde08000 0x0 0x1000>; 3175 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 3176 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 3177 clock-names = "mclk", "hclk"; 3178 assigned-clocks = <&cru MCLK_SPDIFRX0>; 3179 assigned-clock-parents = <&cru PLL_AUPLL>; 3180 dmas = <&dmac0 21>; 3181 dma-names = "rx"; 3182 power-domains = <&power RK3588_PD_VO1>; 3183 resets = <&cru SRST_M_SPDIFRX0>; 3184 reset-names = "spdifrx-m"; 3185 #sound-dai-cells = <0>; 3186 status = "disabled"; 3187 }; 3188 3189 dsi0: dsi@fde20000 { 3190 compatible = "rockchip,rk3588-mipi-dsi2"; 3191 reg = <0x0 0xfde20000 0x0 0x10000>; 3192 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 3193 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 3194 clock-names = "pclk", "sys_clk"; 3195 resets = <&cru SRST_P_DSIHOST0>; 3196 reset-names = "apb"; 3197 power-domains = <&power RK3588_PD_VOP>; 3198 phys = <&mipi_dcphy0>; 3199 phy-names = "dcphy"; 3200 rockchip,grf = <&vop_grf>; 3201 #address-cells = <1>; 3202 #size-cells = <0>; 3203 status = "disabled"; 3204 3205 ports { 3206 #address-cells = <1>; 3207 #size-cells = <0>; 3208 3209 dsi0_in: port@0 { 3210 reg = <0>; 3211 #address-cells = <1>; 3212 #size-cells = <0>; 3213 3214 dsi0_in_vp2: endpoint@0 { 3215 reg = <0>; 3216 remote-endpoint = <&vp2_out_dsi0>; 3217 status = "disabled"; 3218 }; 3219 3220 dsi0_in_vp3: endpoint@1 { 3221 reg = <1>; 3222 remote-endpoint = <&vp3_out_dsi0>; 3223 status = "disabled"; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 dsi1: dsi@fde30000 { 3230 compatible = "rockchip,rk3588-mipi-dsi2"; 3231 reg = <0x0 0xfde30000 0x0 0x10000>; 3232 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 3233 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; 3234 clock-names = "pclk", "sys_clk"; 3235 resets = <&cru SRST_P_DSIHOST1>; 3236 reset-names = "apb"; 3237 power-domains = <&power RK3588_PD_VOP>; 3238 phys = <&mipi_dcphy1>; 3239 phy-names = "dcphy"; 3240 rockchip,grf = <&vop_grf>; 3241 #address-cells = <1>; 3242 #size-cells = <0>; 3243 status = "disabled"; 3244 3245 ports { 3246 #address-cells = <1>; 3247 #size-cells = <0>; 3248 3249 dsi1_in: port@0 { 3250 reg = <0>; 3251 #address-cells = <1>; 3252 #size-cells = <0>; 3253 3254 dsi1_in_vp2: endpoint@0 { 3255 reg = <0>; 3256 remote-endpoint = <&vp2_out_dsi1>; 3257 status = "disabled"; 3258 }; 3259 3260 dsi1_in_vp3: endpoint@1 { 3261 reg = <1>; 3262 remote-endpoint = <&vp3_out_dsi1>; 3263 status = "disabled"; 3264 }; 3265 }; 3266 }; 3267 }; 3268 3269 dp0: dp@fde50000 { 3270 compatible = "rockchip,rk3588-dp"; 3271 reg = <0x0 0xfde50000 0x0 0x4000>; 3272 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 3273 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, <&hclk_vo0>; 3274 clock-names = "apb", "aux", "hclk"; 3275 assigned-clocks = <&cru CLK_AUX16M_0>; 3276 assigned-clock-rates = <16000000>; 3277 resets = <&cru SRST_DP0>; 3278 phys = <&usbdp_phy0_dp>; 3279 power-domains = <&power RK3588_PD_VO0>; 3280 status = "disabled"; 3281 3282 ports { 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 3286 dp0_in: port@0 { 3287 reg = <0>; 3288 #address-cells = <1>; 3289 #size-cells = <0>; 3290 3291 dp0_in_vp0: endpoint@0 { 3292 reg = <0>; 3293 remote-endpoint = <&vp0_out_dp0>; 3294 status = "disabled"; 3295 }; 3296 3297 dp0_in_vp1: endpoint@1 { 3298 reg = <1>; 3299 remote-endpoint = <&vp1_out_dp0>; 3300 status = "disabled"; 3301 }; 3302 3303 dp0_in_vp2: endpoint@2 { 3304 reg = <2>; 3305 remote-endpoint = <&vp2_out_dp0>; 3306 status = "disabled"; 3307 }; 3308 }; 3309 }; 3310 }; 3311 3312 hdmi0: hdmi@fde80000 { 3313 compatible = "rockchip,rk3588-dw-hdmi"; 3314 reg = <0x0 0xfde80000 0x0 0x20000>; 3315 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3320 clocks = <&cru PCLK_HDMITX0>, 3321 <&cru CLK_HDMIHDP0>, 3322 <&cru CLK_HDMITX0_EARC>, 3323 <&cru CLK_HDMITX0_REF>, 3324 <&cru MCLK_I2S5_8CH_TX>, 3325 <&hclk_vo1>; 3326 clock-names = "pclk", "hpd", "earc", "hdmitx_ref", "aud", "hclk_vo1"; 3327 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 3328 reset-names = "ref", "hdp"; 3329 power-domains = <&power RK3588_PD_VO1>; 3330 pinctrl-names = "default"; 3331 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; 3332 reg-io-width = <4>; 3333 rockchip,grf = <&sys_grf>; 3334 rockchip,vo1_grf = <&vo1_grf>; 3335 phys = <&hdptxphy_hdmi0>; 3336 phy-names = "hdmi"; 3337 #sound-dai-cells = <0>; 3338 status = "disabled"; 3339 3340 ports { 3341 #address-cells = <1>; 3342 #size-cells = <0>; 3343 3344 hdmi0_in: port@0 { 3345 reg = <0>; 3346 #address-cells = <1>; 3347 #size-cells = <0>; 3348 3349 hdmi0_in_vp0: endpoint@0 { 3350 reg = <0>; 3351 remote-endpoint = <&vp0_out_hdmi0>; 3352 status = "disabled"; 3353 }; 3354 3355 hdmi0_in_vp1: endpoint@1 { 3356 reg = <1>; 3357 remote-endpoint = <&vp1_out_hdmi0>; 3358 status = "disabled"; 3359 }; 3360 3361 hdmi0_in_vp2: endpoint@2 { 3362 reg = <2>; 3363 remote-endpoint = <&vp2_out_hdmi0>; 3364 status = "disabled"; 3365 }; 3366 }; 3367 }; 3368 }; 3369 3370 edp0: edp@fdec0000 { 3371 compatible = "rockchip,rk3588-edp"; 3372 reg = <0x0 0xfdec0000 0x0 0x1000>; 3373 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3374 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 3375 <&cru CLK_EDP0_200M>, <&hclk_vo1>; 3376 clock-names = "dp", "pclk", "spdif", "hclk"; 3377 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 3378 reset-names = "dp", "apb"; 3379 phys = <&hdptxphy0>; 3380 phy-names = "dp"; 3381 power-domains = <&power RK3588_PD_VO1>; 3382 rockchip,grf = <&vo1_grf>; 3383 status = "disabled"; 3384 3385 ports { 3386 #address-cells = <1>; 3387 #size-cells = <0>; 3388 3389 edp0_in: port@0 { 3390 reg = <0>; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 edp0_in_vp0: endpoint@0 { 3395 reg = <0>; 3396 remote-endpoint = <&vp0_out_edp0>; 3397 status = "disabled"; 3398 }; 3399 3400 edp0_in_vp1: endpoint@1 { 3401 reg = <1>; 3402 remote-endpoint = <&vp1_out_edp0>; 3403 status = "disabled"; 3404 }; 3405 3406 edp0_in_vp2: endpoint@2 { 3407 reg = <2>; 3408 remote-endpoint = <&vp2_out_edp0>; 3409 status = "disabled"; 3410 }; 3411 }; 3412 }; 3413 }; 3414 3415 qos_gpu_m0: qos@fdf35000 { 3416 compatible = "syscon"; 3417 reg = <0x0 0xfdf35000 0x0 0x20>; 3418 }; 3419 3420 qos_gpu_m1: qos@fdf35200 { 3421 compatible = "syscon"; 3422 reg = <0x0 0xfdf35200 0x0 0x20>; 3423 }; 3424 3425 qos_gpu_m2: qos@fdf35400 { 3426 compatible = "syscon"; 3427 reg = <0x0 0xfdf35400 0x0 0x20>; 3428 }; 3429 3430 qos_gpu_m3: qos@fdf35600 { 3431 compatible = "syscon"; 3432 reg = <0x0 0xfdf35600 0x0 0x20>; 3433 }; 3434 3435 qos_rga3_1: qos@fdf36000 { 3436 compatible = "syscon"; 3437 reg = <0x0 0xfdf36000 0x0 0x20>; 3438 }; 3439 3440 qos_sdio: qos@fdf39000 { 3441 compatible = "syscon"; 3442 reg = <0x0 0xfdf39000 0x0 0x20>; 3443 }; 3444 3445 qos_sdmmc: qos@fdf3d800 { 3446 compatible = "syscon"; 3447 reg = <0x0 0xfdf3d800 0x0 0x20>; 3448 }; 3449 3450 qos_usb3_1: qos@fdf3e000 { 3451 compatible = "syscon"; 3452 reg = <0x0 0xfdf3e000 0x0 0x20>; 3453 }; 3454 3455 qos_usb3_0: qos@fdf3e200 { 3456 compatible = "syscon"; 3457 reg = <0x0 0xfdf3e200 0x0 0x20>; 3458 }; 3459 3460 qos_usb2host_0: qos@fdf3e400 { 3461 compatible = "syscon"; 3462 reg = <0x0 0xfdf3e400 0x0 0x20>; 3463 }; 3464 3465 qos_usb2host_1: qos@fdf3e600 { 3466 compatible = "syscon"; 3467 reg = <0x0 0xfdf3e600 0x0 0x20>; 3468 }; 3469 3470 qos_fisheye0: qos@fdf40000 { 3471 compatible = "syscon"; 3472 reg = <0x0 0xfdf40000 0x0 0x20>; 3473 }; 3474 3475 qos_fisheye1: qos@fdf40200 { 3476 compatible = "syscon"; 3477 reg = <0x0 0xfdf40200 0x0 0x20>; 3478 }; 3479 3480 qos_isp0_mro: qos@fdf40400 { 3481 compatible = "syscon"; 3482 reg = <0x0 0xfdf40400 0x0 0x20>; 3483 }; 3484 3485 qos_isp0_mwo: qos@fdf40500 { 3486 compatible = "syscon"; 3487 reg = <0x0 0xfdf40500 0x0 0x20>; 3488 }; 3489 3490 qos_vicap_m0: qos@fdf40600 { 3491 compatible = "syscon"; 3492 reg = <0x0 0xfdf40600 0x0 0x20>; 3493 }; 3494 3495 qos_vicap_m1: qos@fdf40800 { 3496 compatible = "syscon"; 3497 reg = <0x0 0xfdf40800 0x0 0x20>; 3498 }; 3499 3500 qos_isp1_mwo: qos@fdf41000 { 3501 compatible = "syscon"; 3502 reg = <0x0 0xfdf41000 0x0 0x20>; 3503 }; 3504 3505 qos_isp1_mro: qos@fdf41100 { 3506 compatible = "syscon"; 3507 reg = <0x0 0xfdf41100 0x0 0x20>; 3508 }; 3509 3510 qos_rkvenc0_m0ro: qos@fdf60000 { 3511 compatible = "syscon"; 3512 reg = <0x0 0xfdf60000 0x0 0x20>; 3513 }; 3514 3515 qos_rkvenc0_m1ro: qos@fdf60200 { 3516 compatible = "syscon"; 3517 reg = <0x0 0xfdf60200 0x0 0x20>; 3518 }; 3519 3520 qos_rkvenc0_m2wo: qos@fdf60400 { 3521 compatible = "syscon"; 3522 reg = <0x0 0xfdf60400 0x0 0x20>; 3523 }; 3524 3525 qos_rkvenc1_m0ro: qos@fdf61000 { 3526 compatible = "syscon"; 3527 reg = <0x0 0xfdf61000 0x0 0x20>; 3528 }; 3529 3530 qos_rkvenc1_m1ro: qos@fdf61200 { 3531 compatible = "syscon"; 3532 reg = <0x0 0xfdf61200 0x0 0x20>; 3533 }; 3534 3535 qos_rkvenc1_m2wo: qos@fdf61400 { 3536 compatible = "syscon"; 3537 reg = <0x0 0xfdf61400 0x0 0x20>; 3538 }; 3539 3540 qos_rkvdec0: qos@fdf62000 { 3541 compatible = "syscon"; 3542 reg = <0x0 0xfdf62000 0x0 0x20>; 3543 }; 3544 3545 qos_rkvdec1: qos@fdf63000 { 3546 compatible = "syscon"; 3547 reg = <0x0 0xfdf63000 0x0 0x20>; 3548 }; 3549 3550 qos_av1: qos@fdf64000 { 3551 compatible = "syscon"; 3552 reg = <0x0 0xfdf64000 0x0 0x20>; 3553 }; 3554 3555 qos_iep: qos@fdf66000 { 3556 compatible = "syscon"; 3557 reg = <0x0 0xfdf66000 0x0 0x20>; 3558 }; 3559 3560 qos_jpeg_dec: qos@fdf66200 { 3561 compatible = "syscon"; 3562 reg = <0x0 0xfdf66200 0x0 0x20>; 3563 }; 3564 3565 qos_jpeg_enc0: qos@fdf66400 { 3566 compatible = "syscon"; 3567 reg = <0x0 0xfdf66400 0x0 0x20>; 3568 }; 3569 3570 qos_jpeg_enc1: qos@fdf66600 { 3571 compatible = "syscon"; 3572 reg = <0x0 0xfdf66600 0x0 0x20>; 3573 }; 3574 3575 qos_jpeg_enc2: qos@fdf66800 { 3576 compatible = "syscon"; 3577 reg = <0x0 0xfdf66800 0x0 0x20>; 3578 }; 3579 3580 qos_jpeg_enc3: qos@fdf66a00 { 3581 compatible = "syscon"; 3582 reg = <0x0 0xfdf66a00 0x0 0x20>; 3583 }; 3584 3585 qos_rga2_mro: qos@fdf66c00 { 3586 compatible = "syscon"; 3587 reg = <0x0 0xfdf66c00 0x0 0x20>; 3588 }; 3589 3590 qos_rga2_mwo: qos@fdf66e00 { 3591 compatible = "syscon"; 3592 reg = <0x0 0xfdf66e00 0x0 0x20>; 3593 }; 3594 3595 qos_rga3_0: qos@fdf67000 { 3596 compatible = "syscon"; 3597 reg = <0x0 0xfdf67000 0x0 0x20>; 3598 }; 3599 3600 qos_vdpu: qos@fdf67200 { 3601 compatible = "syscon"; 3602 reg = <0x0 0xfdf67200 0x0 0x20>; 3603 }; 3604 3605 qos_npu1: qos@fdf70000 { 3606 compatible = "syscon"; 3607 reg = <0x0 0xfdf70000 0x0 0x20>; 3608 }; 3609 3610 qos_npu2: qos@fdf71000 { 3611 compatible = "syscon"; 3612 reg = <0x0 0xfdf71000 0x0 0x20>; 3613 }; 3614 3615 qos_npu0_mwr: qos@fdf72000 { 3616 compatible = "syscon"; 3617 reg = <0x0 0xfdf72000 0x0 0x20>; 3618 }; 3619 3620 qos_npu0_mro: qos@fdf72200 { 3621 compatible = "syscon"; 3622 reg = <0x0 0xfdf72200 0x0 0x20>; 3623 }; 3624 3625 qos_mcu_npu: qos@fdf72400 { 3626 compatible = "syscon"; 3627 reg = <0x0 0xfdf72400 0x0 0x20>; 3628 }; 3629 3630 qos_hdcp0: qos@fdf80000 { 3631 compatible = "syscon"; 3632 reg = <0x0 0xfdf80000 0x0 0x20>; 3633 }; 3634 3635 qos_hdcp1: qos@fdf81000 { 3636 compatible = "syscon"; 3637 reg = <0x0 0xfdf81000 0x0 0x20>; 3638 }; 3639 3640 qos_hdmirx: qos@fdf81200 { 3641 compatible = "syscon"; 3642 reg = <0x0 0xfdf81200 0x0 0x20>; 3643 }; 3644 3645 qos_vop_m0: qos@fdf82000 { 3646 compatible = "syscon"; 3647 reg = <0x0 0xfdf82000 0x0 0x20>; 3648 }; 3649 3650 qos_vop_m1: qos@fdf82200 { 3651 compatible = "syscon"; 3652 reg = <0x0 0xfdf82200 0x0 0x20>; 3653 }; 3654 3655 dfi: dfi@fe060000 { 3656 reg = <0x00 0xfe060000 0x00 0x10000>; 3657 compatible = "rockchip,rk3588-dfi"; 3658 rockchip,pmu_grf = <&pmu1_grf>; 3659 status = "disabled"; 3660 }; 3661 3662 pcie2x1l1: pcie@fe180000 { 3663 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 3664 #address-cells = <3>; 3665 #size-cells = <2>; 3666 bus-range = <0x30 0x3f>; 3667 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 3668 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 3669 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 3670 clock-names = "aclk_mst", "aclk_slv", 3671 "aclk_dbi", "pclk", 3672 "aux", "pipe"; 3673 device_type = "pci"; 3674 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 3679 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 3680 #interrupt-cells = <1>; 3681 interrupt-map-mask = <0 0 0 7>; 3682 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 3683 <0 0 0 2 &pcie2x1l1_intc 1>, 3684 <0 0 0 3 &pcie2x1l1_intc 2>, 3685 <0 0 0 4 &pcie2x1l1_intc 3>; 3686 linux,pci-domain = <3>; 3687 num-ib-windows = <8>; 3688 num-ob-windows = <8>; 3689 num-viewport = <4>; 3690 max-link-speed = <2>; 3691 msi-map = <0x3000 &its0 0x3000 0x1000>; 3692 num-lanes = <1>; 3693 phys = <&combphy2_psu PHY_TYPE_PCIE>; 3694 phy-names = "pcie-phy"; 3695 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 3696 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 3697 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 3698 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 3699 reg = <0x0 0xfe180000 0x0 0x10000>, 3700 <0xa 0x40c00000 0x0 0x400000>; 3701 reg-names = "pcie-apb", "pcie-dbi"; 3702 resets = <&cru SRST_PCIE3_POWER_UP>; 3703 reset-names = "pipe"; 3704 rockchip,pipe-grf = <&php_grf>; 3705 status = "disabled"; 3706 3707 pcie2x1l1_intc: legacy-interrupt-controller { 3708 interrupt-controller; 3709 #address-cells = <0>; 3710 #interrupt-cells = <1>; 3711 interrupt-parent = <&gic>; 3712 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 3713 }; 3714 }; 3715 3716 pcie2x1l2: pcie@fe190000 { 3717 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 3718 #address-cells = <3>; 3719 #size-cells = <2>; 3720 bus-range = <0x40 0x4f>; 3721 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 3722 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 3723 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 3724 clock-names = "aclk_mst", "aclk_slv", 3725 "aclk_dbi", "pclk", 3726 "aux", "pipe"; 3727 device_type = "pci"; 3728 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 3733 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 3734 #interrupt-cells = <1>; 3735 interrupt-map-mask = <0 0 0 7>; 3736 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 3737 <0 0 0 2 &pcie2x1l2_intc 1>, 3738 <0 0 0 3 &pcie2x1l2_intc 2>, 3739 <0 0 0 4 &pcie2x1l2_intc 3>; 3740 linux,pci-domain = <4>; 3741 num-ib-windows = <8>; 3742 num-ob-windows = <8>; 3743 num-viewport = <4>; 3744 max-link-speed = <2>; 3745 msi-map = <0x4000 &its0 0x4000 0x1000>; 3746 num-lanes = <1>; 3747 phys = <&combphy0_ps PHY_TYPE_PCIE>; 3748 phy-names = "pcie-phy"; 3749 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 3750 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 3751 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 3752 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 3753 reg = <0x0 0xfe190000 0x0 0x10000>, 3754 <0xa 0x41000000 0x0 0x400000>; 3755 reg-names = "pcie-apb", "pcie-dbi"; 3756 resets = <&cru SRST_PCIE4_POWER_UP>; 3757 reset-names = "pipe"; 3758 rockchip,pipe-grf = <&php_grf>; 3759 status = "disabled"; 3760 3761 pcie2x1l2_intc: legacy-interrupt-controller { 3762 interrupt-controller; 3763 #address-cells = <0>; 3764 #interrupt-cells = <1>; 3765 interrupt-parent = <&gic>; 3766 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 3767 }; 3768 }; 3769 3770 gmac1: ethernet@fe1c0000 { 3771 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 3772 reg = <0x0 0xfe1c0000 0x0 0x10000>; 3773 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 3775 interrupt-names = "macirq", "eth_wake_irq"; 3776 rockchip,grf = <&sys_grf>; 3777 rockchip,php_grf = <&php_grf>; 3778 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 3779 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 3780 <&cru CLK_GMAC1_PTP_REF>; 3781 clock-names = "stmmaceth", "clk_mac_ref", 3782 "pclk_mac", "aclk_mac", 3783 "ptp_ref"; 3784 resets = <&cru SRST_A_GMAC1>; 3785 reset-names = "stmmaceth"; 3786 power-domains = <&power RK3588_PD_GMAC>; 3787 3788 snps,mixed-burst; 3789 snps,tso; 3790 3791 snps,axi-config = <&gmac1_stmmac_axi_setup>; 3792 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 3793 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 3794 status = "disabled"; 3795 3796 mdio1: mdio { 3797 compatible = "snps,dwmac-mdio"; 3798 #address-cells = <0x1>; 3799 #size-cells = <0x0>; 3800 }; 3801 3802 gmac1_stmmac_axi_setup: stmmac-axi-config { 3803 snps,wr_osr_lmt = <4>; 3804 snps,rd_osr_lmt = <8>; 3805 snps,blen = <0 0 0 0 16 8 4>; 3806 }; 3807 3808 gmac1_mtl_rx_setup: rx-queues-config { 3809 snps,rx-queues-to-use = <2>; 3810 queue0 {}; 3811 queue1 {}; 3812 }; 3813 3814 gmac1_mtl_tx_setup: tx-queues-config { 3815 snps,tx-queues-to-use = <2>; 3816 queue0 {}; 3817 queue1 {}; 3818 }; 3819 }; 3820 3821 sata0: sata@fe210000 { 3822 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3823 reg = <0 0xfe210000 0 0x1000>; 3824 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 3825 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 3826 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 3827 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 3828 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 3829 interrupt-names = "hostc"; 3830 phys = <&combphy0_ps PHY_TYPE_SATA>; 3831 phy-names = "sata-phy"; 3832 ports-implemented = <0x1>; 3833 status = "disabled"; 3834 }; 3835 3836 sata2: sata@fe230000 { 3837 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 3838 reg = <0 0xfe230000 0 0x1000>; 3839 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 3840 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 3841 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 3842 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 3843 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 3844 interrupt-names = "hostc"; 3845 phys = <&combphy2_psu PHY_TYPE_SATA>; 3846 phy-names = "sata-phy"; 3847 ports-implemented = <0x1>; 3848 status = "disabled"; 3849 }; 3850 3851 sfc: spi@fe2b0000 { 3852 compatible = "rockchip,sfc"; 3853 reg = <0x0 0xfe2b0000 0x0 0x4000>; 3854 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 3855 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 3856 clock-names = "clk_sfc", "hclk_sfc"; 3857 assigned-clocks = <&cru SCLK_SFC>; 3858 assigned-clock-rates = <100000000>; 3859 #address-cells = <1>; 3860 #size-cells = <0>; 3861 status = "disabled"; 3862 }; 3863 3864 sdmmc: mmc@fe2c0000 { 3865 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 3866 reg = <0x0 0xfe2c0000 0x0 0x4000>; 3867 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 3868 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 3869 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 3870 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 3871 fifo-depth = <0x100>; 3872 max-frequency = <200000000>; 3873 pinctrl-names = "default"; 3874 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 3875 power-domains = <&power RK3588_PD_SDMMC>; 3876 status = "disabled"; 3877 }; 3878 3879 sdio: mmc@fe2d0000 { 3880 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 3881 reg = <0x0 0xfe2d0000 0x0 0x4000>; 3882 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 3883 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 3884 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 3885 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 3886 fifo-depth = <0x100>; 3887 max-frequency = <200000000>; 3888 pinctrl-names = "default"; 3889 pinctrl-0 = <&sdiom1_pins>; 3890 power-domains = <&power RK3588_PD_SDIO>; 3891 status = "disabled"; 3892 }; 3893 3894 sdhci: mmc@fe2e0000 { 3895 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 3896 reg = <0x0 0xfe2e0000 0x0 0x10000>; 3897 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 3898 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 3899 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 3900 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 3901 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 3902 <&cru TMCLK_EMMC>; 3903 clock-names = "core", "bus", "axi", "block", "timer"; 3904 max-frequency = <200000000>; 3905 status = "disabled"; 3906 }; 3907 3908 crypto: crypto@fe370000 { 3909 compatible = "rockchip,rk3588-crypto"; 3910 reg = <0x0 0xfe370000 0x0 0x2000>; 3911 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 3912 clocks = <&scmi_clk SCMI_ACLK_SECURE_NS>, <&scmi_clk SCMI_HCLK_SECURE_NS>, 3913 <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; 3914 clock-names = "aclk", "hclk", "sclk", "pka"; 3915 resets = <&scmi_reset SRST_CRYPTO_CORE>; 3916 reset-names = "crypto-rst"; 3917 status = "disabled"; 3918 }; 3919 3920 rng: rng@fe378000 { 3921 compatible = "rockchip,trngv1"; 3922 reg = <0x0 0xfe378000 0x0 0x200>; 3923 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 3924 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 3925 clock-names = "hclk_trng"; 3926 resets = <&scmi_reset SRST_H_TRNG_NS>; 3927 reset-names = "reset"; 3928 status = "disabled"; 3929 }; 3930 3931 i2s0_8ch: i2s@fe470000 { 3932 compatible = "rockchip,rk3588-i2s-tdm"; 3933 reg = <0x0 0xfe470000 0x0 0x1000>; 3934 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 3935 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 3936 clock-names = "mclk_tx", "mclk_rx", "hclk"; 3937 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 3938 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 3939 dmas = <&dmac0 0>, <&dmac0 1>; 3940 dma-names = "tx", "rx"; 3941 power-domains = <&power RK3588_PD_AUDIO>; 3942 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 3943 reset-names = "tx-m", "rx-m"; 3944 rockchip,clk-trcm = <1>; 3945 pinctrl-names = "default"; 3946 pinctrl-0 = <&i2s0_lrck 3947 &i2s0_sclk 3948 &i2s0_sdi0 3949 &i2s0_sdi1 3950 &i2s0_sdi2 3951 &i2s0_sdi3 3952 &i2s0_sdo0 3953 &i2s0_sdo1 3954 &i2s0_sdo2 3955 &i2s0_sdo3>; 3956 #sound-dai-cells = <0>; 3957 status = "disabled"; 3958 }; 3959 3960 i2s1_8ch: i2s@fe480000 { 3961 compatible = "rockchip,rk3588-i2s-tdm"; 3962 reg = <0x0 0xfe480000 0x0 0x1000>; 3963 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 3964 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 3965 clock-names = "mclk_tx", "mclk_rx", "hclk"; 3966 dmas = <&dmac0 2>, <&dmac0 3>; 3967 dma-names = "tx", "rx"; 3968 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 3969 reset-names = "tx-m", "rx-m"; 3970 rockchip,clk-trcm = <1>; 3971 pinctrl-names = "default"; 3972 pinctrl-0 = <&i2s1m0_lrck 3973 &i2s1m0_sclk 3974 &i2s1m0_sdi0 3975 &i2s1m0_sdi1 3976 &i2s1m0_sdi2 3977 &i2s1m0_sdi3 3978 &i2s1m0_sdo0 3979 &i2s1m0_sdo1 3980 &i2s1m0_sdo2 3981 &i2s1m0_sdo3>; 3982 #sound-dai-cells = <0>; 3983 status = "disabled"; 3984 }; 3985 3986 i2s2_2ch: i2s@fe490000 { 3987 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 3988 reg = <0x0 0xfe490000 0x0 0x1000>; 3989 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 3990 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 3991 clock-names = "i2s_clk", "i2s_hclk"; 3992 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 3993 assigned-clock-parents = <&cru PLL_AUPLL>; 3994 dmas = <&dmac1 0>, <&dmac1 1>; 3995 dma-names = "tx", "rx"; 3996 power-domains = <&power RK3588_PD_AUDIO>; 3997 rockchip,clk-trcm = <1>; 3998 pinctrl-names = "default"; 3999 pinctrl-0 = <&i2s2m1_lrck 4000 &i2s2m1_sclk 4001 &i2s2m1_sdi 4002 &i2s2m1_sdo>; 4003 #sound-dai-cells = <0>; 4004 status = "disabled"; 4005 }; 4006 4007 i2s3_2ch: i2s@fe4a0000 { 4008 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 4009 reg = <0x0 0xfe4a0000 0x0 0x1000>; 4010 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 4011 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 4012 clock-names = "i2s_clk", "i2s_hclk"; 4013 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 4014 assigned-clock-parents = <&cru PLL_AUPLL>; 4015 dmas = <&dmac1 2>, <&dmac1 3>; 4016 dma-names = "tx", "rx"; 4017 power-domains = <&power RK3588_PD_AUDIO>; 4018 rockchip,clk-trcm = <1>; 4019 pinctrl-names = "default"; 4020 pinctrl-0 = <&i2s3_lrck 4021 &i2s3_sclk 4022 &i2s3_sdi 4023 &i2s3_sdo>; 4024 #sound-dai-cells = <0>; 4025 status = "disabled"; 4026 }; 4027 4028 pdm0: pdm@fe4b0000 { 4029 compatible = "rockchip,rk3588-pdm"; 4030 reg = <0x0 0xfe4b0000 0x0 0x1000>; 4031 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 4032 clock-names = "pdm_clk", "pdm_hclk"; 4033 dmas = <&dmac0 4>; 4034 dma-names = "rx"; 4035 pinctrl-names = "default"; 4036 pinctrl-0 = <&pdm0m0_clk 4037 &pdm0m0_clk1 4038 &pdm0m0_sdi0 4039 &pdm0m0_sdi1 4040 &pdm0m0_sdi2 4041 &pdm0m0_sdi3>; 4042 #sound-dai-cells = <0>; 4043 status = "disabled"; 4044 }; 4045 4046 pdm1: pdm@fe4c0000 { 4047 compatible = "rockchip,rk3588-pdm"; 4048 reg = <0x0 0xfe4c0000 0x0 0x1000>; 4049 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 4050 clock-names = "pdm_clk", "pdm_hclk"; 4051 assigned-clocks = <&cru MCLK_PDM1>; 4052 assigned-clock-parents = <&cru PLL_AUPLL>; 4053 dmas = <&dmac1 4>; 4054 dma-names = "rx"; 4055 power-domains = <&power RK3588_PD_AUDIO>; 4056 pinctrl-names = "default"; 4057 pinctrl-0 = <&pdm1m0_clk 4058 &pdm1m0_clk1 4059 &pdm1m0_sdi0 4060 &pdm1m0_sdi1 4061 &pdm1m0_sdi2 4062 &pdm1m0_sdi3>; 4063 #sound-dai-cells = <0>; 4064 status = "disabled"; 4065 }; 4066 4067 vad: vad@fe4d0000 { 4068 compatible = "rockchip,rk3588-vad"; 4069 reg = <0x0 0xfe4d0000 0x0 0x1000>; 4070 reg-names = "vad"; 4071 clocks = <&cru HCLK_VAD>; 4072 clock-names = "hclk"; 4073 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 4074 rockchip,audio-src = <0>; 4075 rockchip,det-channel = <0>; 4076 rockchip,mode = <0>; 4077 #sound-dai-cells = <0>; 4078 status = "disabled"; 4079 }; 4080 4081 spdif_tx0: spdif-tx@fe4e0000 { 4082 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 4083 reg = <0x0 0xfe4e0000 0x0 0x1000>; 4084 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 4085 dmas = <&dmac0 5>; 4086 dma-names = "tx"; 4087 clock-names = "mclk", "hclk"; 4088 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 4089 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 4090 assigned-clock-parents = <&cru PLL_AUPLL>; 4091 power-domains = <&power RK3588_PD_AUDIO>; 4092 pinctrl-names = "default"; 4093 pinctrl-0 = <&spdif0m0_tx>; 4094 #sound-dai-cells = <0>; 4095 status = "disabled"; 4096 }; 4097 4098 spdif_tx1: spdif-tx@fe4f0000 { 4099 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 4100 reg = <0x0 0xfe4f0000 0x0 0x1000>; 4101 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 4102 dmas = <&dmac1 5>; 4103 dma-names = "tx"; 4104 clock-names = "mclk", "hclk"; 4105 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 4106 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 4107 assigned-clock-parents = <&cru PLL_AUPLL>; 4108 power-domains = <&power RK3588_PD_AUDIO>; 4109 pinctrl-names = "default"; 4110 pinctrl-0 = <&spdif1m0_tx>; 4111 #sound-dai-cells = <0>; 4112 status = "disabled"; 4113 }; 4114 4115 acdcdig_dsm: codec-digital@fe500000 { 4116 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 4117 reg = <0x0 0xfe500000 0x0 0x1000>; 4118 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 4119 clock-names = "dac", "pclk"; 4120 power-domains = <&power RK3588_PD_AUDIO>; 4121 resets = <&cru SRST_DAC_ACDCDIG>; 4122 reset-names = "reset" ; 4123 rockchip,grf = <&sys_grf>; 4124 rockchip,pwm-output-mode; 4125 pinctrl-names = "default"; 4126 pinctrl-0 = <&auddsm_pins>; 4127 #sound-dai-cells = <0>; 4128 status = "disabled"; 4129 }; 4130 4131 hwlock: hwspinlock@fe5a0000 { 4132 compatible = "rockchip,hwspinlock"; 4133 reg = <0 0xfe5a0000 0 0x100>; 4134 #hwlock-cells = <1>; 4135 }; 4136 4137 gic: interrupt-controller@fe600000 { 4138 compatible = "arm,gic-v3"; 4139 #interrupt-cells = <3>; 4140 #address-cells = <2>; 4141 #size-cells = <2>; 4142 ranges; 4143 interrupt-controller; 4144 4145 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 4146 <0x0 0xfe680000 0 0x100000>; /* GICR */ 4147 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4148 its0: msi-controller@fe640000 { 4149 compatible = "arm,gic-v3-its"; 4150 msi-controller; 4151 #msi-cells = <1>; 4152 reg = <0x0 0xfe640000 0x0 0x20000>; 4153 }; 4154 its1: msi-controller@fe660000 { 4155 compatible = "arm,gic-v3-its"; 4156 msi-controller; 4157 #msi-cells = <1>; 4158 reg = <0x0 0xfe660000 0x0 0x20000>; 4159 }; 4160 }; 4161 4162 dmac0: dma-controller@fea10000 { 4163 compatible = "arm,pl330", "arm,primecell"; 4164 reg = <0x0 0xfea10000 0x0 0x4000>; 4165 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4167 clocks = <&cru ACLK_DMAC0>; 4168 clock-names = "apb_pclk"; 4169 #dma-cells = <1>; 4170 arm,pl330-periph-burst; 4171 }; 4172 4173 dmac1: dma-controller@fea30000 { 4174 compatible = "arm,pl330", "arm,primecell"; 4175 reg = <0x0 0xfea30000 0x0 0x4000>; 4176 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 4178 clocks = <&cru ACLK_DMAC1>; 4179 clock-names = "apb_pclk"; 4180 #dma-cells = <1>; 4181 arm,pl330-periph-burst; 4182 }; 4183 4184 can0: can@fea50000 { 4185 compatible = "rockchip,can-2.0"; 4186 reg = <0x0 0xfea50000 0x0 0x1000>; 4187 iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 4188 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 4189 clock-names = "baudclk", "apb_pclk"; 4190 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 4191 reset-names = "can", "can-apb"; 4192 pinctrl-names = "default"; 4193 pinctrl-0 = <&can0m0_pins>; 4194 tx-fifo-depth = <1>; 4195 rx-fifo-depth = <6>; 4196 status = "disabled"; 4197 }; 4198 4199 can1: can@fea60000 { 4200 compatible = "rockchip,can-2.0"; 4201 reg = <0x0 0xfea60000 0x0 0x1000>; 4202 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 4203 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 4204 clock-names = "baudclk", "apb_pclk"; 4205 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 4206 reset-names = "can", "can-apb"; 4207 pinctrl-names = "default"; 4208 pinctrl-0 = <&can1m0_pins>; 4209 tx-fifo-depth = <1>; 4210 rx-fifo-depth = <6>; 4211 status = "disabled"; 4212 }; 4213 4214 can2: can@fea70000 { 4215 compatible = "rockchip,can-2.0"; 4216 reg = <0x0 0xfea70000 0x0 0x1000>; 4217 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4218 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 4219 clock-names = "baudclk", "apb_pclk"; 4220 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 4221 reset-names = "can", "can-apb"; 4222 pinctrl-names = "default"; 4223 pinctrl-0 = <&can2m0_pins>; 4224 tx-fifo-depth = <1>; 4225 rx-fifo-depth = <6>; 4226 status = "disabled"; 4227 }; 4228 4229 hw_decompress: decompress@fea80000 { 4230 compatible = "rockchip,hw-decompress"; 4231 reg = <0x0 0xfea80000 0x0 0x1000>; 4232 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 4233 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 4234 clock-names = "aclk", "dclk", "pclk"; 4235 resets = <&cru SRST_D_DECOM>; 4236 reset-names = "dresetn"; 4237 status = "disabled"; 4238 }; 4239 4240 i2c1: i2c@fea90000 { 4241 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4242 reg = <0x0 0xfea90000 0x0 0x1000>; 4243 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 4244 clock-names = "i2c", "pclk"; 4245 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 4246 pinctrl-names = "default"; 4247 pinctrl-0 = <&i2c1m0_xfer>; 4248 #address-cells = <1>; 4249 #size-cells = <0>; 4250 status = "disabled"; 4251 }; 4252 4253 i2c2: i2c@feaa0000 { 4254 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4255 reg = <0x0 0xfeaa0000 0x0 0x1000>; 4256 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 4257 clock-names = "i2c", "pclk"; 4258 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 4259 pinctrl-names = "default"; 4260 pinctrl-0 = <&i2c2m0_xfer>; 4261 #address-cells = <1>; 4262 #size-cells = <0>; 4263 status = "disabled"; 4264 }; 4265 4266 i2c3: i2c@feab0000 { 4267 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4268 reg = <0x0 0xfeab0000 0x0 0x1000>; 4269 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 4270 clock-names = "i2c", "pclk"; 4271 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 4272 pinctrl-names = "default"; 4273 pinctrl-0 = <&i2c3m0_xfer>; 4274 #address-cells = <1>; 4275 #size-cells = <0>; 4276 status = "disabled"; 4277 }; 4278 4279 i2c4: i2c@feac0000 { 4280 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4281 reg = <0x0 0xfeac0000 0x0 0x1000>; 4282 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 4283 clock-names = "i2c", "pclk"; 4284 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 4285 pinctrl-names = "default"; 4286 pinctrl-0 = <&i2c4m0_xfer>; 4287 #address-cells = <1>; 4288 #size-cells = <0>; 4289 status = "disabled"; 4290 }; 4291 4292 i2c5: i2c@fead0000 { 4293 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4294 reg = <0x0 0xfead0000 0x0 0x1000>; 4295 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 4296 clock-names = "i2c", "pclk"; 4297 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 4298 pinctrl-names = "default"; 4299 pinctrl-0 = <&i2c5m0_xfer>; 4300 #address-cells = <1>; 4301 #size-cells = <0>; 4302 status = "disabled"; 4303 }; 4304 4305 rktimer: timer@feae0000 { 4306 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 4307 reg = <0x0 0xfeae0000 0x0 0x20>; 4308 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 4309 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 4310 clock-names = "pclk", "timer"; 4311 }; 4312 4313 wdt: watchdog@feaf0000 { 4314 compatible = "snps,dw-wdt"; 4315 reg = <0x0 0xfeaf0000 0x0 0x100>; 4316 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 4317 clock-names = "tclk", "pclk"; 4318 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 4319 status = "okay"; 4320 }; 4321 4322 spi0: spi@feb00000 { 4323 compatible = "rockchip,rk3066-spi"; 4324 reg = <0x0 0xfeb00000 0x0 0x1000>; 4325 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 4326 #address-cells = <1>; 4327 #size-cells = <0>; 4328 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 4329 clock-names = "spiclk", "apb_pclk"; 4330 dmas = <&dmac0 14>, <&dmac0 15>; 4331 dma-names = "tx", "rx"; 4332 pinctrl-names = "default"; 4333 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 4334 num-cs = <2>; 4335 status = "disabled"; 4336 }; 4337 4338 spi1: spi@feb10000 { 4339 compatible = "rockchip,rk3066-spi"; 4340 reg = <0x0 0xfeb10000 0x0 0x1000>; 4341 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 4342 #address-cells = <1>; 4343 #size-cells = <0>; 4344 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 4345 clock-names = "spiclk", "apb_pclk"; 4346 dmas = <&dmac0 16>, <&dmac0 17>; 4347 dma-names = "tx", "rx"; 4348 pinctrl-names = "default"; 4349 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 4350 num-cs = <2>; 4351 status = "disabled"; 4352 }; 4353 4354 spi2: spi@feb20000 { 4355 compatible = "rockchip,rk3066-spi"; 4356 reg = <0x0 0xfeb20000 0x0 0x1000>; 4357 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 4358 #address-cells = <1>; 4359 #size-cells = <0>; 4360 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 4361 clock-names = "spiclk", "apb_pclk"; 4362 dmas = <&dmac1 15>, <&dmac1 16>; 4363 dma-names = "tx", "rx"; 4364 pinctrl-names = "default"; 4365 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 4366 num-cs = <2>; 4367 status = "disabled"; 4368 }; 4369 4370 spi3: spi@feb30000 { 4371 compatible = "rockchip,rk3066-spi"; 4372 reg = <0x0 0xfeb30000 0x0 0x1000>; 4373 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 4374 #address-cells = <1>; 4375 #size-cells = <0>; 4376 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 4377 clock-names = "spiclk", "apb_pclk"; 4378 dmas = <&dmac1 17>, <&dmac1 18>; 4379 dma-names = "tx", "rx"; 4380 pinctrl-names = "default"; 4381 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 4382 num-cs = <2>; 4383 status = "disabled"; 4384 }; 4385 4386 uart1: serial@feb40000 { 4387 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4388 reg = <0x0 0xfeb40000 0x0 0x100>; 4389 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 4390 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 4391 clock-names = "baudclk", "apb_pclk"; 4392 reg-shift = <2>; 4393 reg-io-width = <4>; 4394 dmas = <&dmac0 8>, <&dmac0 9>; 4395 pinctrl-names = "default"; 4396 pinctrl-0 = <&uart1m1_xfer>; 4397 status = "disabled"; 4398 }; 4399 4400 uart2: serial@feb50000 { 4401 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4402 reg = <0x0 0xfeb50000 0x0 0x100>; 4403 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 4404 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 4405 clock-names = "baudclk", "apb_pclk"; 4406 reg-shift = <2>; 4407 reg-io-width = <4>; 4408 dmas = <&dmac0 10>, <&dmac0 11>; 4409 pinctrl-names = "default"; 4410 pinctrl-0 = <&uart2m1_xfer>; 4411 status = "disabled"; 4412 }; 4413 4414 uart3: serial@feb60000 { 4415 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4416 reg = <0x0 0xfeb60000 0x0 0x100>; 4417 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 4418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 4419 clock-names = "baudclk", "apb_pclk"; 4420 reg-shift = <2>; 4421 reg-io-width = <4>; 4422 dmas = <&dmac0 12>, <&dmac0 13>; 4423 pinctrl-names = "default"; 4424 pinctrl-0 = <&uart3m1_xfer>; 4425 status = "disabled"; 4426 }; 4427 4428 uart4: serial@feb70000 { 4429 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4430 reg = <0x0 0xfeb70000 0x0 0x100>; 4431 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 4432 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 4433 clock-names = "baudclk", "apb_pclk"; 4434 reg-shift = <2>; 4435 reg-io-width = <4>; 4436 dmas = <&dmac1 9>, <&dmac1 10>; 4437 pinctrl-names = "default"; 4438 pinctrl-0 = <&uart4m1_xfer>; 4439 status = "disabled"; 4440 }; 4441 4442 uart5: serial@feb80000 { 4443 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4444 reg = <0x0 0xfeb80000 0x0 0x100>; 4445 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 4446 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 4447 clock-names = "baudclk", "apb_pclk"; 4448 reg-shift = <2>; 4449 reg-io-width = <4>; 4450 dmas = <&dmac1 11>, <&dmac1 12>; 4451 pinctrl-names = "default"; 4452 pinctrl-0 = <&uart5m1_xfer>; 4453 status = "disabled"; 4454 }; 4455 4456 uart6: serial@feb90000 { 4457 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4458 reg = <0x0 0xfeb90000 0x0 0x100>; 4459 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 4460 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 4461 clock-names = "baudclk", "apb_pclk"; 4462 reg-shift = <2>; 4463 reg-io-width = <4>; 4464 dmas = <&dmac1 13>, <&dmac1 14>; 4465 pinctrl-names = "default"; 4466 pinctrl-0 = <&uart6m1_xfer>; 4467 status = "disabled"; 4468 }; 4469 4470 uart7: serial@feba0000 { 4471 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4472 reg = <0x0 0xfeba0000 0x0 0x100>; 4473 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 4474 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 4475 clock-names = "baudclk", "apb_pclk"; 4476 reg-shift = <2>; 4477 reg-io-width = <4>; 4478 dmas = <&dmac2 7>, <&dmac2 8>; 4479 pinctrl-names = "default"; 4480 pinctrl-0 = <&uart7m1_xfer>; 4481 status = "disabled"; 4482 }; 4483 4484 uart8: serial@febb0000 { 4485 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4486 reg = <0x0 0xfebb0000 0x0 0x100>; 4487 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 4488 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 4489 clock-names = "baudclk", "apb_pclk"; 4490 reg-shift = <2>; 4491 reg-io-width = <4>; 4492 dmas = <&dmac2 9>, <&dmac2 10>; 4493 pinctrl-names = "default"; 4494 pinctrl-0 = <&uart8m1_xfer>; 4495 status = "disabled"; 4496 }; 4497 4498 uart9: serial@febc0000 { 4499 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 4500 reg = <0x0 0xfebc0000 0x0 0x100>; 4501 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 4502 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 4503 clock-names = "baudclk", "apb_pclk"; 4504 reg-shift = <2>; 4505 reg-io-width = <4>; 4506 dmas = <&dmac2 11>, <&dmac2 12>; 4507 pinctrl-names = "default"; 4508 pinctrl-0 = <&uart9m1_xfer>; 4509 status = "disabled"; 4510 }; 4511 4512 pwm4: pwm@febd0000 { 4513 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4514 reg = <0x0 0xfebd0000 0x0 0x10>; 4515 #pwm-cells = <3>; 4516 pinctrl-names = "active"; 4517 pinctrl-0 = <&pwm4m0_pins>; 4518 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4519 clock-names = "pwm", "pclk"; 4520 status = "disabled"; 4521 }; 4522 4523 pwm5: pwm@febd0010 { 4524 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4525 reg = <0x0 0xfebd0010 0x0 0x10>; 4526 #pwm-cells = <3>; 4527 pinctrl-names = "active"; 4528 pinctrl-0 = <&pwm5m0_pins>; 4529 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4530 clock-names = "pwm", "pclk"; 4531 status = "disabled"; 4532 }; 4533 4534 pwm6: pwm@febd0020 { 4535 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4536 reg = <0x0 0xfebd0020 0x0 0x10>; 4537 #pwm-cells = <3>; 4538 pinctrl-names = "active"; 4539 pinctrl-0 = <&pwm6m0_pins>; 4540 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4541 clock-names = "pwm", "pclk"; 4542 status = "disabled"; 4543 }; 4544 4545 pwm7: pwm@febd0030 { 4546 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4547 reg = <0x0 0xfebd0030 0x0 0x10>; 4548 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4549 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 4550 #pwm-cells = <3>; 4551 pinctrl-names = "active"; 4552 pinctrl-0 = <&pwm7m0_pins>; 4553 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 4554 clock-names = "pwm", "pclk"; 4555 status = "disabled"; 4556 }; 4557 4558 pwm8: pwm@febe0000 { 4559 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4560 reg = <0x0 0xfebe0000 0x0 0x10>; 4561 #pwm-cells = <3>; 4562 pinctrl-names = "active"; 4563 pinctrl-0 = <&pwm8m0_pins>; 4564 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4565 clock-names = "pwm", "pclk"; 4566 status = "disabled"; 4567 }; 4568 4569 pwm9: pwm@febe0010 { 4570 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4571 reg = <0x0 0xfebe0010 0x0 0x10>; 4572 #pwm-cells = <3>; 4573 pinctrl-names = "active"; 4574 pinctrl-0 = <&pwm9m0_pins>; 4575 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4576 clock-names = "pwm", "pclk"; 4577 status = "disabled"; 4578 }; 4579 4580 pwm10: pwm@febe0020 { 4581 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4582 reg = <0x0 0xfebe0020 0x0 0x10>; 4583 #pwm-cells = <3>; 4584 pinctrl-names = "active"; 4585 pinctrl-0 = <&pwm10m0_pins>; 4586 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4587 clock-names = "pwm", "pclk"; 4588 status = "disabled"; 4589 }; 4590 4591 pwm11: pwm@febe0030 { 4592 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4593 reg = <0x0 0xfebe0030 0x0 0x10>; 4594 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 4596 #pwm-cells = <3>; 4597 pinctrl-names = "active"; 4598 pinctrl-0 = <&pwm11m0_pins>; 4599 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 4600 clock-names = "pwm", "pclk"; 4601 status = "disabled"; 4602 }; 4603 4604 pwm12: pwm@febf0000 { 4605 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4606 reg = <0x0 0xfebf0000 0x0 0x10>; 4607 #pwm-cells = <3>; 4608 pinctrl-names = "active"; 4609 pinctrl-0 = <&pwm12m0_pins>; 4610 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 4611 clock-names = "pwm", "pclk"; 4612 status = "disabled"; 4613 }; 4614 4615 pwm13: pwm@febf0010 { 4616 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4617 reg = <0x0 0xfebf0010 0x0 0x10>; 4618 #pwm-cells = <3>; 4619 pinctrl-names = "active"; 4620 pinctrl-0 = <&pwm13m0_pins>; 4621 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 4622 clock-names = "pwm", "pclk"; 4623 status = "disabled"; 4624 }; 4625 4626 pwm14: pwm@febf0020 { 4627 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4628 reg = <0x0 0xfebf0020 0x0 0x10>; 4629 #pwm-cells = <3>; 4630 pinctrl-names = "active"; 4631 pinctrl-0 = <&pwm14m0_pins>; 4632 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 4633 clock-names = "pwm", "pclk"; 4634 status = "disabled"; 4635 }; 4636 4637 pwm15: pwm@febf0030 { 4638 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 4639 reg = <0x0 0xfebf0030 0x0 0x10>; 4640 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 4641 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 4642 #pwm-cells = <3>; 4643 pinctrl-names = "active"; 4644 pinctrl-0 = <&pwm15m0_pins>; 4645 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 4646 clock-names = "pwm", "pclk"; 4647 status = "disabled"; 4648 }; 4649 4650 tsadc: tsadc@fec00000 { 4651 compatible = "rockchip,rk3588-tsadc"; 4652 reg = <0x0 0xfec00000 0x0 0x400>; 4653 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 4654 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 4655 clock-names = "tsadc", "apb_pclk"; 4656 assigned-clocks = <&cru CLK_TSADC>; 4657 assigned-clock-rates = <2000000>; 4658 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 4659 reset-names = "tsadc", "tsadc-apb"; 4660 #thermal-sensor-cells = <1>; 4661 rockchip,hw-tshut-temp = <120000>; 4662 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 4663 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 4664 pinctrl-names = "gpio", "otpout"; 4665 pinctrl-0 = <&tsadc_gpio_func>; 4666 pinctrl-1 = <&tsadc_shut>; 4667 status = "disabled"; 4668 }; 4669 4670 saradc: saradc@fec10000 { 4671 compatible = "rockchip,rk3588-saradc"; 4672 reg = <0x0 0xfec10000 0x0 0x10000>; 4673 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 4674 #io-channel-cells = <1>; 4675 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 4676 clock-names = "saradc", "apb_pclk"; 4677 resets = <&cru SRST_P_SARADC>; 4678 reset-names = "saradc-apb"; 4679 status = "disabled"; 4680 }; 4681 4682 mailbox0: mailbox@fec60000 { 4683 compatible = "rockchip,rk3588-mailbox", 4684 "rockchip,rk3368-mailbox"; 4685 reg = <0x0 0xfec60000 0x0 0x200>; 4686 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 4690 clocks = <&cru PCLK_MAILBOX0>; 4691 clock-names = "pclk_mailbox"; 4692 #mbox-cells = <1>; 4693 status = "disabled"; 4694 }; 4695 4696 mailbox1: mailbox@fec70000 { 4697 compatible = "rockchip,rk3588-mailbox", 4698 "rockchip,rk3368-mailbox"; 4699 reg = <0x0 0xfec70000 0x0 0x200>; 4700 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4704 clocks = <&cru PCLK_MAILBOX1>; 4705 clock-names = "pclk_mailbox"; 4706 #mbox-cells = <1>; 4707 status = "disabled"; 4708 }; 4709 4710 i2c6: i2c@fec80000 { 4711 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4712 reg = <0x0 0xfec80000 0x0 0x1000>; 4713 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 4714 clock-names = "i2c", "pclk"; 4715 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 4716 pinctrl-names = "default"; 4717 pinctrl-0 = <&i2c6m0_xfer>; 4718 #address-cells = <1>; 4719 #size-cells = <0>; 4720 status = "disabled"; 4721 }; 4722 4723 i2c7: i2c@fec90000 { 4724 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4725 reg = <0x0 0xfec90000 0x0 0x1000>; 4726 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 4727 clock-names = "i2c", "pclk"; 4728 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 4729 pinctrl-names = "default"; 4730 pinctrl-0 = <&i2c7m0_xfer>; 4731 #address-cells = <1>; 4732 #size-cells = <0>; 4733 status = "disabled"; 4734 }; 4735 4736 i2c8: i2c@feca0000 { 4737 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 4738 reg = <0x0 0xfeca0000 0x0 0x1000>; 4739 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 4740 clock-names = "i2c", "pclk"; 4741 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 4742 pinctrl-names = "default"; 4743 pinctrl-0 = <&i2c8m0_xfer>; 4744 #address-cells = <1>; 4745 #size-cells = <0>; 4746 status = "disabled"; 4747 }; 4748 4749 spi4: spi@fecb0000 { 4750 compatible = "rockchip,rk3066-spi"; 4751 reg = <0x0 0xfecb0000 0x0 0x1000>; 4752 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 4753 #address-cells = <1>; 4754 #size-cells = <0>; 4755 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 4756 clock-names = "spiclk", "apb_pclk"; 4757 dmas = <&dmac2 13>, <&dmac2 14>; 4758 dma-names = "tx", "rx"; 4759 pinctrl-names = "default"; 4760 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 4761 num-cs = <2>; 4762 status = "disabled"; 4763 }; 4764 4765 otp: otp@fecc0000 { 4766 compatible = "rockchip,rk3588-otp"; 4767 reg = <0x0 0xfecc0000 0x0 0x400>; 4768 #address-cells = <1>; 4769 #size-cells = <1>; 4770 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 4771 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 4772 clock-names = "otpc", "apb", "arb", "phy"; 4773 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 4774 <&cru SRST_OTPC_ARB>; 4775 reset-names = "otpc", "apb", "arb"; 4776 4777 /* Data cells */ 4778 cpu_code: cpu-code@2 { 4779 reg = <0x02 0x2>; 4780 }; 4781 otp_id: id@7 { 4782 reg = <0x07 0x10>; 4783 }; 4784 otp_cpu_version: cpu-version@1c { 4785 reg = <0x1c 0x1>; 4786 bits = <3 3>; 4787 }; 4788 }; 4789 4790 mailbox2: mailbox@fece0000 { 4791 compatible = "rockchip,rk3588-mailbox", 4792 "rockchip,rk3368-mailbox"; 4793 reg = <0x0 0xfece0000 0x0 0x200>; 4794 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 4795 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 4796 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 4797 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 4798 clocks = <&cru PCLK_MAILBOX2>; 4799 clock-names = "pclk_mailbox"; 4800 #mbox-cells = <1>; 4801 status = "disabled"; 4802 }; 4803 4804 dmac2: dma-controller@fed10000 { 4805 compatible = "arm,pl330", "arm,primecell"; 4806 reg = <0x0 0xfed10000 0x0 0x4000>; 4807 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 4808 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 4809 clocks = <&cru ACLK_DMAC2>; 4810 clock-names = "apb_pclk"; 4811 #dma-cells = <1>; 4812 arm,pl330-periph-burst; 4813 }; 4814 4815 hdptxphy0: phy@fed60000 { 4816 compatible = "rockchip,rk3588-hdptx-phy"; 4817 reg = <0x0 0xfed60000 0x0 0x2000>; 4818 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 4819 clock-names = "ref", "apb"; 4820 resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, 4821 <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>; 4822 reset-names = "apb", "init", "cmn", "lane"; 4823 rockchip,grf = <&hdptxphy0_grf>; 4824 #phy-cells = <0>; 4825 status = "disabled"; 4826 }; 4827 4828 hdptxphy_hdmi0: hdmiphy@fed60000 { 4829 compatible = "rockchip,rk3588-hdptx-phy-hdmi"; 4830 reg = <0x0 0xfed60000 0x0 0x2000>; 4831 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 4832 clock-names = "ref", "apb"; 4833 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 4834 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 4835 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 4836 <&cru SRST_HDPTX0_LCPLL>; 4837 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 4838 "lcpll"; 4839 rockchip,grf = <&hdptxphy0_grf>; 4840 #phy-cells = <0>; 4841 #clock-cells = <0>; 4842 status = "disabled"; 4843 }; 4844 4845 usbdp_phy0: phy@fed80000 { 4846 compatible = "rockchip,rk3588-usbdp-phy"; 4847 reg = <0x0 0xfed80000 0x0 0x10000>; 4848 rockchip,u2phy-grf = <&usb2phy0_grf>; 4849 rockchip,usb-grf = <&usb_grf>; 4850 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 4851 rockchip,vo-grf = <&vo0_grf>; 4852 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 4853 <&cru CLK_USBDP_PHY0_IMMORTAL>, 4854 <&cru PCLK_USBDPPHY0>, 4855 <&u2phy0>; 4856 clock-names = "refclk", "immortal", "pclk", "utmi"; 4857 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 4858 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 4859 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 4860 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 4861 <&cru SRST_P_USBDPPHY0>; 4862 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 4863 status = "disabled"; 4864 4865 usbdp_phy0_dp: dp-port { 4866 #phy-cells = <0>; 4867 status = "disabled"; 4868 }; 4869 4870 usbdp_phy0_u3: u3-port { 4871 #phy-cells = <0>; 4872 status = "disabled"; 4873 }; 4874 }; 4875 4876 mipi_dcphy0: phy@feda0000 { 4877 compatible = "rockchip,rk3588-mipi-dcphy"; 4878 reg = <0x0 0xfeda0000 0x0 0xb00>; 4879 rockchip,grf = <&mipidcphy0_grf>; 4880 clocks = <&cru PCLK_MIPI_DCPHY0>, 4881 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 4882 clock-names = "pclk", "ref"; 4883 resets = <&cru SRST_M_MIPI_DCPHY0>, 4884 <&cru SRST_P_MIPI_DCPHY0>, 4885 <&cru SRST_P_MIPI_DCPHY0_GRF>; 4886 reset-names = "phy", "apb", "grf"; 4887 #phy-cells = <0>; 4888 status = "disabled"; 4889 }; 4890 4891/* 4892 mipi_dcphy0: phy@feda0000 { 4893 compatible = "rockchip,rk3588-mipi-dcphy"; 4894 reg = <0x0 0xfeda0000 0x0 0x10000>; 4895 rockchip,grf = <&mipidcphy0_grf>; 4896 clocks = <&cru PCLK_MIPI_DCPHY0>, 4897 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 4898 clock-names = "pclk", "ref"; 4899 resets = <&cru SRST_M_MIPI_DCPHY0>, 4900 <&cru SRST_P_MIPI_DCPHY0>, 4901 <&cru SRST_P_MIPI_DCPHY0_GRF>, 4902 <&cru SRST_S_MIPI_DCPHY0>; 4903 reset-names = "m_phy", "apb", "grf", "s_phy"; 4904 #phy-cells = <0>; 4905 status = "disabled"; 4906 }; 4907*/ 4908 4909 csi2_dcphy0_hw: csi2-dcphy0-hw@feda0b00 { 4910 compatible = "rockchip,rk3588-csi2-dcphy-hw"; 4911 reg = <0x0 0xfeda0b00 0x0 0xf500>; 4912 clocks = <&cru PCLK_MIPI_DCPHY0>; 4913 clock-names = "pclk"; 4914 resets = <&cru SRST_S_MIPI_DCPHY0>; 4915 reset-names = "phy"; 4916 rockchip,grf = <&mipidcphy0_grf>; 4917 status = "disabled"; 4918 }; 4919 4920 mipi_dcphy1: phy@fedb0000 { 4921 compatible = "rockchip,rk3588-mipi-dcphy"; 4922 reg = <0x0 0xfedb0000 0x0 0xb00>; 4923 rockchip,grf = <&mipidcphy1_grf>; 4924 clocks = <&cru PCLK_MIPI_DCPHY1>, 4925 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 4926 clock-names = "pclk", "ref"; 4927 resets = <&cru SRST_M_MIPI_DCPHY1>, 4928 <&cru SRST_P_MIPI_DCPHY1>, 4929 <&cru SRST_P_MIPI_DCPHY1_GRF>; 4930 reset-names = "phy", "apb", "grf"; 4931 #phy-cells = <0>; 4932 status = "disabled"; 4933 }; 4934 4935 csi2_dcphy1_hw: csi2-dcphy1-hw@fedb0b00 { 4936 compatible = "rockchip,rk3588-csi2-dcphy-hw"; 4937 reg = <0x0 0xfedb0b00 0x0 0xf500>; 4938 clocks = <&cru PCLK_MIPI_DCPHY1>; 4939 clock-names = "pclk"; 4940 resets = <&cru SRST_S_MIPI_DCPHY1>; 4941 reset-names = "phy"; 4942 rockchip,grf = <&mipidcphy1_grf>; 4943 status = "disabled"; 4944 }; 4945 4946 csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 { 4947 compatible = "rockchip,rk3588-csi2-dphy-hw"; 4948 reg = <0x0 0xfedc0000 0x0 0x8000>; 4949 clocks = <&cru PCLK_CSIPHY0>; 4950 clock-names = "pclk"; 4951 resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>; 4952 reset-names = "srst_csiphy0", "srst_p_csiphy0"; 4953 rockchip,grf = <&mipidphy0_grf>; 4954 rockchip,sys_grf = <&sys_grf>; 4955 status = "disabled"; 4956 }; 4957 4958 combphy0_ps: phy@fee00000 { 4959 compatible = "rockchip,rk3588-naneng-combphy"; 4960 reg = <0x0 0xfee00000 0x0 0x100>; 4961 #phy-cells = <1>; 4962 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 4963 <&cru PCLK_PHP_ROOT>; 4964 clock-names = "refclk", "apbclk", "phpclk"; 4965 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 4966 assigned-clock-rates = <100000000>; 4967 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 4968 reset-names = "combphy-apb", "combphy"; 4969 rockchip,pipe-grf = <&php_grf>; 4970 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 4971 status = "disabled"; 4972 }; 4973 4974 combphy2_psu: phy@fee20000 { 4975 compatible = "rockchip,rk3588-naneng-combphy"; 4976 reg = <0x0 0xfee20000 0x0 0x100>; 4977 #phy-cells = <1>; 4978 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 4979 <&cru PCLK_PHP_ROOT>; 4980 clock-names = "refclk", "apbclk", "phpclk"; 4981 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 4982 assigned-clock-rates = <100000000>; 4983 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 4984 reset-names = "combphy-apb", "combphy"; 4985 rockchip,pipe-grf = <&php_grf>; 4986 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 4987 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 4988 status = "disabled"; 4989 }; 4990 4991 pinctrl: pinctrl { 4992 compatible = "rockchip,rk3588-pinctrl"; 4993 rockchip,grf = <&ioc>; 4994 #address-cells = <2>; 4995 #size-cells = <2>; 4996 ranges; 4997 4998 gpio0: gpio@fd8a0000 { 4999 compatible = "rockchip,gpio-bank"; 5000 reg = <0x0 0xfd8a0000 0x0 0x100>; 5001 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 5002 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 5003 5004 gpio-controller; 5005 #gpio-cells = <2>; 5006 gpio-ranges = <&pinctrl 0 0 32>; 5007 interrupt-controller; 5008 #interrupt-cells = <2>; 5009 }; 5010 5011 gpio1: gpio@fec20000 { 5012 compatible = "rockchip,gpio-bank"; 5013 reg = <0x0 0xfec20000 0x0 0x100>; 5014 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 5015 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 5016 5017 gpio-controller; 5018 #gpio-cells = <2>; 5019 gpio-ranges = <&pinctrl 0 32 32>; 5020 interrupt-controller; 5021 #interrupt-cells = <2>; 5022 }; 5023 5024 gpio2: gpio@fec30000 { 5025 compatible = "rockchip,gpio-bank"; 5026 reg = <0x0 0xfec30000 0x0 0x100>; 5027 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 5028 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 5029 5030 gpio-controller; 5031 #gpio-cells = <2>; 5032 gpio-ranges = <&pinctrl 0 64 32>; 5033 interrupt-controller; 5034 #interrupt-cells = <2>; 5035 }; 5036 5037 gpio3: gpio@fec40000 { 5038 compatible = "rockchip,gpio-bank"; 5039 reg = <0x0 0xfec40000 0x0 0x100>; 5040 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 5041 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 5042 5043 gpio-controller; 5044 #gpio-cells = <2>; 5045 gpio-ranges = <&pinctrl 0 96 32>; 5046 interrupt-controller; 5047 #interrupt-cells = <2>; 5048 }; 5049 5050 gpio4: gpio@fec50000 { 5051 compatible = "rockchip,gpio-bank"; 5052 reg = <0x0 0xfec50000 0x0 0x100>; 5053 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 5054 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 5055 5056 gpio-controller; 5057 #gpio-cells = <2>; 5058 gpio-ranges = <&pinctrl 0 128 32>; 5059 interrupt-controller; 5060 #interrupt-cells = <2>; 5061 }; 5062 }; 5063}; 5064 5065#include "rk3588s-pinctrl.dtsi" 5066
