1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip usb PHY driver
4 *
5 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
6 * Copyright (C) 2014 ROCKCHIP, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/extcon-provider.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/reset.h>
28 #include <linux/regmap.h>
29 #include <linux/usb/of.h>
30 #include <linux/wakelock.h>
31
32 static int enable_usb_uart;
33
34 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
35
36 #define UOC_CON0 0x00
37 #define UOC_CON0_SIDDQ BIT(13)
38 #define UOC_CON0_DISABLE BIT(4)
39 #define UOC_CON0_COMMON_ON_N BIT(0)
40
41 #define UOC_CON2 0x08
42 #define UOC_CON2_SOFT_CON_SEL BIT(2)
43
44 #define UOC_CON3 0x0c
45 /* bits present on rk3188 and rk3288 phys */
46 #define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
47 #define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
48 #define UOC_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
49 #define UOC_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
50 #define UOC_CON3_UTMI_OPMODE_MASK (3 << 1)
51 #define UOC_CON3_UTMI_SUSPENDN BIT(0)
52
53 #define RK3288_UOC0_CON0 0x320
54 #define RK3288_UOC0_CON0_COMMON_ON_N BIT(0)
55 #define RK3288_UOC0_CON0_DISABLE BIT(4)
56
57 #define RK3288_UOC0_CON2 0x328
58 #define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2)
59 #define RK3288_UOC0_CON2_CHRGSEL BIT(5)
60 #define RK3288_UOC0_CON2_VDATDETENB BIT(6)
61 #define RK3288_UOC0_CON2_VDATSRCENB BIT(7)
62 #define RK3288_UOC0_CON2_DCDENB BIT(14)
63
64 #define RK3288_UOC0_CON3 0x32c
65 #define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0)
66 #define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING BIT(1)
67 #define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1)
68 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC BIT(3)
69 #define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
70 #define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
71 #define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
72 #define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
73 #define RK3288_UOC0_CON3_IDDIG_SET_OTG (0 << 12)
74 #define RK3288_UOC0_CON3_IDDIG_SET_HOST (2 << 12)
75 #define RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL (3 << 12)
76 #define RK3288_UOC0_CON3_IDDIG_SET_MASK (3 << 12)
77
78 #define RK3288_UOC0_CON4 0x330
79 #define RK3288_UOC0_CON4_BVALID_IRQ_EN BIT(2)
80 #define RK3288_UOC0_CON4_BVALID_IRQ_PD BIT(3)
81
82 #define RK3288_SOC_STATUS2 0x288
83 #define RK3288_SOC_STATUS2_UTMISRP_BVALID BIT(14)
84 #define RK3288_SOC_STATUS2_UTMIOTG_IDDIG BIT(17)
85
86 #define RK3288_SOC_STATUS19 0x2cc
87 #define RK3288_SOC_STATUS19_CHGDET BIT(23)
88 #define RK3288_SOC_STATUS19_FSVPLUS BIT(24)
89 #define RK3288_SOC_STATUS19_FSVMINUS BIT(25)
90
91 #define OTG_SCHEDULE_DELAY (1 * HZ)
92 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
93 #define CHG_DCD_MAX_RETRIES 6
94 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
95 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
96
97 #define PHY_ROCKCHIP_USB_RECALC_RATE 480000000
98 #define UDELAY_TEN 10
99 #define PHY_ROCKCHIP_USB_PRIMARY_RETRIES 2
100 #define PHY_ROCKCHIP_USB_BIT 16
101
102 enum usb_chg_state {
103 USB_CHG_STATE_UNDEFINED = 0,
104 USB_CHG_STATE_WAIT_FOR_DCD,
105 USB_CHG_STATE_DCD_DONE,
106 USB_CHG_STATE_PRIMARY_DONE,
107 USB_CHG_STATE_SECONDARY_DONE,
108 USB_CHG_STATE_DETECTED,
109 };
110
111 static const unsigned int rockchip_usb_phy_extcon_cable[] = {
112 EXTCON_USB, EXTCON_USB_HOST, EXTCON_USB_VBUS_EN, EXTCON_CHG_USB_SDP,
113 EXTCON_CHG_USB_CDP, EXTCON_CHG_USB_DCP, EXTCON_NONE,
114 };
115
116 struct rockchip_usb_phys {
117 int reg;
118 const char *pll_name;
119 };
120
121 struct rockchip_usb_phy_base;
122 struct rockchip_usb_phy_pdata {
123 struct rockchip_usb_phys *phys;
124 int (*init_usb_uart)(struct regmap *grf, const struct rockchip_usb_phy_pdata *pdata);
125 int usb_uart_phy;
126 };
127
128 struct rockchip_usb_phy_base {
129 struct device *dev;
130 struct regmap *reg_base;
131 struct extcon_dev *edev;
132 const struct rockchip_usb_phy_pdata *pdata;
133 };
134
135 struct rockchip_usb_phy {
136 struct rockchip_usb_phy_base *base;
137 struct device_node *np;
138 unsigned int reg_offset;
139 struct clk *clk;
140 struct clk *clk480m;
141 struct clk_hw clk480m_hw;
142 struct phy *phy;
143 bool uart_enabled;
144 int bvalid_irq;
145 struct reset_control *reset;
146 struct regulator *vbus;
147 struct mutex mutex; /* protects registers of phy */
148 struct delayed_work chg_work;
149 struct delayed_work otg_sm_work;
150 struct wake_lock wakelock;
151 enum usb_chg_state chg_state;
152 enum power_supply_type chg_type;
153 enum usb_dr_mode mode;
154 };
155
otg_mode_show(struct device * dev,struct device_attribute * attr,char * buf)156 static ssize_t otg_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
157 {
158 struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
159
160 if (!rk_phy) {
161 dev_err(dev, "Fail to get otg phy.\n");
162 return -EINVAL;
163 }
164
165 switch (rk_phy->mode) {
166 case USB_DR_MODE_HOST:
167 return sprintf(buf, "host\n");
168 case USB_DR_MODE_PERIPHERAL:
169 return sprintf(buf, "peripheral\n");
170 case USB_DR_MODE_OTG:
171 return sprintf(buf, "otg\n");
172 case USB_DR_MODE_UNKNOWN:
173 return sprintf(buf, "UNKNOWN\n");
174 default:
175 break;
176 }
177
178 return -EINVAL;
179 }
180
otg_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)181 static ssize_t otg_mode_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
182 {
183 struct rockchip_usb_phy *rk_phy = dev_get_drvdata(dev);
184 enum usb_dr_mode new_dr_mode;
185 int ret = count;
186 int val = 0;
187
188 if (!rk_phy) {
189 dev_err(dev, "Fail to get otg phy.\n");
190 return -EINVAL;
191 }
192
193 mutex_lock(&rk_phy->mutex);
194
195 if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
196 new_dr_mode = USB_DR_MODE_OTG;
197 } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
198 new_dr_mode = USB_DR_MODE_HOST;
199 } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
200 new_dr_mode = USB_DR_MODE_PERIPHERAL;
201 } else {
202 dev_err(&rk_phy->phy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
203 ret = -EINVAL;
204 goto out_unlock;
205 }
206
207 if (rk_phy->mode == new_dr_mode) {
208 dev_warn(&rk_phy->phy->dev, "Same as current mode.\n");
209 goto out_unlock;
210 }
211
212 rk_phy->mode = new_dr_mode;
213
214 switch (rk_phy->mode) {
215 case USB_DR_MODE_HOST:
216 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST, RK3288_UOC0_CON3_IDDIG_SET_MASK);
217 break;
218 case USB_DR_MODE_PERIPHERAL:
219 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL, RK3288_UOC0_CON3_IDDIG_SET_MASK);
220 break;
221 case USB_DR_MODE_OTG:
222 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG, RK3288_UOC0_CON3_IDDIG_SET_MASK);
223 break;
224 default:
225 break;
226 }
227
228 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
229
230 out_unlock:
231 mutex_unlock(&rk_phy->mutex);
232
233 return ret;
234 }
235
236 static DEVICE_ATTR_RW(otg_mode);
237
238 /* Group all the usb2 phy attributes */
239 static struct attribute *usb2_phy_attrs[] = {
240 &dev_attr_otg_mode.attr,
241 NULL,
242 };
243
244 static struct attribute_group usb2_phy_attr_group = {
245 .name = NULL, /* we want them in the same directory */
246 .attrs = usb2_phy_attrs,
247 };
248
rockchip_usb_phy_power(struct rockchip_usb_phy * phy,bool siddq)249 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, bool siddq)
250 {
251 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
252
253 return regmap_write(phy->base->reg_base, phy->reg_offset, val);
254 }
255
rockchip_usb_phy480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)256 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
257 {
258 return PHY_ROCKCHIP_USB_RECALC_RATE;
259 }
260
rockchip_usb_phy480m_disable(struct clk_hw * hw)261 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
262 {
263 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw);
264
265 if (phy->vbus) {
266 regulator_disable(phy->vbus);
267 }
268
269 /* Power down usb phy analog blocks by set siddq 1 */
270 rockchip_usb_phy_power(phy, 1);
271 }
272
rockchip_usb_phy480m_enable(struct clk_hw * hw)273 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
274 {
275 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw);
276
277 /* Power up usb phy analog blocks by set siddq 0 */
278 return rockchip_usb_phy_power(phy, 0);
279 }
280
rockchip_usb_phy480m_is_enabled(struct clk_hw * hw)281 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
282 {
283 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw);
284 int ret;
285 u32 val;
286
287 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
288 if (ret < 0) {
289 return ret;
290 }
291
292 return (val & UOC_CON0_SIDDQ) ? 0 : 1;
293 }
294
295 static const struct clk_ops rockchip_usb_phy480m_ops = {
296 .enable = rockchip_usb_phy480m_enable,
297 .disable = rockchip_usb_phy480m_disable,
298 .is_enabled = rockchip_usb_phy480m_is_enabled,
299 .recalc_rate = rockchip_usb_phy480m_recalc_rate,
300 };
301
rk3288_usb_phy_init(struct phy * _phy)302 static int rk3288_usb_phy_init(struct phy *_phy)
303 {
304 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
305 int ret = 0;
306 unsigned int val;
307
308 if (phy->bvalid_irq > 0) {
309 mutex_lock(&phy->mutex);
310
311 /* clear bvalid status and enable bvalid detect irq */
312 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_EN | RK3288_UOC0_CON4_BVALID_IRQ_PD,
313 RK3288_UOC0_CON4_BVALID_IRQ_EN | RK3288_UOC0_CON4_BVALID_IRQ_PD);
314 ret = regmap_write(phy->base->reg_base, RK3288_UOC0_CON4, val);
315 if (ret) {
316 dev_err(phy->base->dev, "failed to enable bvalid irq\n");
317 goto out;
318 }
319
320 schedule_delayed_work(&phy->otg_sm_work, OTG_SCHEDULE_DELAY);
321
322 out:
323 mutex_unlock(&phy->mutex);
324 }
325
326 return ret;
327 }
328
rk3288_usb_phy_exit(struct phy * _phy)329 static int rk3288_usb_phy_exit(struct phy *_phy)
330 {
331 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
332
333 if (phy->bvalid_irq > 0) {
334 flush_delayed_work(&phy->otg_sm_work);
335 }
336
337 return 0;
338 }
339
rockchip_usb_phy_power_off(struct phy * _phy)340 static int rockchip_usb_phy_power_off(struct phy *_phy)
341 {
342 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
343
344 if (phy->uart_enabled) {
345 return -EBUSY;
346 }
347
348 clk_disable_unprepare(phy->clk480m);
349
350 return 0;
351 }
352
rockchip_usb_phy_power_on(struct phy * _phy)353 static int rockchip_usb_phy_power_on(struct phy *_phy)
354 {
355 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
356
357 if (phy->uart_enabled) {
358 return -EBUSY;
359 }
360
361 if (phy->vbus) {
362 int ret;
363
364 ret = regulator_enable(phy->vbus);
365 if (ret) {
366 return ret;
367 }
368 }
369
370 return clk_prepare_enable(phy->clk480m);
371 }
372
rockchip_usb_phy_reset(struct phy * _phy)373 static int rockchip_usb_phy_reset(struct phy *_phy)
374 {
375 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
376
377 if (phy->reset) {
378 reset_control_assert(phy->reset);
379 udelay(UDELAY_TEN);
380 reset_control_deassert(phy->reset);
381 }
382
383 return 0;
384 }
385
386 static struct phy_ops ops = {
387 .power_on = rockchip_usb_phy_power_on,
388 .power_off = rockchip_usb_phy_power_off,
389 .reset = rockchip_usb_phy_reset,
390 .owner = THIS_MODULE,
391 };
392
rockchip_usb_phy_action(void * data)393 static void rockchip_usb_phy_action(void *data)
394 {
395 struct rockchip_usb_phy *rk_phy = data;
396
397 if (!rk_phy->uart_enabled) {
398 of_clk_del_provider(rk_phy->np);
399 clk_unregister(rk_phy->clk480m);
400 }
401
402 if (rk_phy->clk) {
403 clk_put(rk_phy->clk);
404 }
405 }
406
rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base * base)407 static int rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base *base)
408 {
409 int ret;
410 struct device_node *node = base->dev->of_node;
411 struct extcon_dev *edev;
412
413 if (of_property_read_bool(node, "extcon")) {
414 edev = extcon_get_edev_by_phandle(base->dev, 0);
415 if (IS_ERR(edev)) {
416 if (PTR_ERR(edev) != -EPROBE_DEFER) {
417 dev_err(base->dev, "Invalid or missing extcon\n");
418 }
419 return PTR_ERR(edev);
420 }
421 } else {
422 /* Initialize extcon device */
423 edev = devm_extcon_dev_allocate(base->dev, rockchip_usb_phy_extcon_cable);
424 if (IS_ERR(edev)) {
425 return -ENOMEM;
426 }
427 ret = devm_extcon_dev_register(base->dev, edev);
428 if (ret) {
429 dev_err(base->dev, "failed to register extcon device\n");
430 return ret;
431 }
432 }
433
434 base->edev = edev;
435
436 return 0;
437 }
438
rk3288_usb_phy_otg_sm_work(struct work_struct * work)439 static void rk3288_usb_phy_otg_sm_work(struct work_struct *work)
440 {
441 struct rockchip_usb_phy *rk_phy = container_of(work, struct rockchip_usb_phy, otg_sm_work.work);
442 unsigned int val;
443 static unsigned int cable;
444 static bool chg_det_completed;
445 bool sch_work;
446 bool vbus_attached;
447 bool id;
448 mutex_lock(&rk_phy->mutex);
449 sch_work = false;
450 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
451 id = (val & RK3288_SOC_STATUS2_UTMIOTG_IDDIG) ? true : false;
452 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS2, &val);
453 vbus_attached = (val & RK3288_SOC_STATUS2_UTMISRP_BVALID) ? true : false;
454 if (!vbus_attached || !id || rk_phy->mode == USB_DR_MODE_HOST) {
455 dev_dbg(&rk_phy->phy->dev, "peripheral disconnected\n");
456 wake_unlock(&rk_phy->wakelock);
457 extcon_set_state_sync(rk_phy->base->edev, cable, false);
458 rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
459 chg_det_completed = false;
460 goto out;
461 }
462 if (chg_det_completed) {
463 sch_work = true;
464 goto out;
465 }
466
467 switch (rk_phy->chg_state) {
468 case USB_CHG_STATE_UNDEFINED:
469 mutex_unlock(&rk_phy->mutex);
470 schedule_delayed_work(&rk_phy->chg_work, 0);
471 return;
472 case USB_CHG_STATE_DETECTED:
473 switch (rk_phy->chg_type) {
474 case POWER_SUPPLY_TYPE_USB:
475 dev_dbg(&rk_phy->phy->dev, "sdp cable is connected\n");
476 wake_lock(&rk_phy->wakelock);
477 cable = EXTCON_CHG_USB_SDP;
478 sch_work = true;
479 break;
480 case POWER_SUPPLY_TYPE_USB_DCP:
481 dev_dbg(&rk_phy->phy->dev, "dcp cable is connected\n");
482 cable = EXTCON_CHG_USB_DCP;
483 sch_work = true;
484 break;
485 case POWER_SUPPLY_TYPE_USB_CDP:
486 dev_dbg(&rk_phy->phy->dev, "cdp cable is connected\n");
487 wake_lock(&rk_phy->wakelock);
488 cable = EXTCON_CHG_USB_CDP;
489 sch_work = true;
490 break;
491 default:
492 break;
493 }
494 chg_det_completed = true;
495 break;
496 default:
497 break;
498 }
499
500 if (extcon_get_state(rk_phy->base->edev, cable) != vbus_attached) {
501 extcon_set_state_sync(rk_phy->base->edev, cable, vbus_attached);
502 }
503
504 out:
505 if (sch_work) {
506 schedule_delayed_work(&rk_phy->otg_sm_work, OTG_SCHEDULE_DELAY);
507 }
508
509 mutex_unlock(&rk_phy->mutex);
510 }
511
chg_to_string(enum power_supply_type chg_type)512 static const char *chg_to_string(enum power_supply_type chg_type)
513 {
514 switch (chg_type) {
515 case POWER_SUPPLY_TYPE_USB:
516 return "USB_SDP_CHARGER";
517 case POWER_SUPPLY_TYPE_USB_DCP:
518 return "USB_DCP_CHARGER";
519 case POWER_SUPPLY_TYPE_USB_CDP:
520 return "USB_CDP_CHARGER";
521 default:
522 return "INVALID_CHARGER";
523 }
524 }
525
rk3288_chg_detect_work(struct work_struct * work)526 static void rk3288_chg_detect_work(struct work_struct *work)
527 {
528 struct rockchip_usb_phy *rk_phy = container_of(work, struct rockchip_usb_phy, chg_work.work);
529 unsigned int val;
530 static int dcd_retries;
531 static int primary_retries;
532 unsigned long delay;
533 bool fsvplus;
534 bool vout;
535 bool tmout;
536
537 dev_dbg(&rk_phy->phy->dev, "chg detection work state = %d\n", rk_phy->chg_state);
538
539 switch (rk_phy->chg_state) {
540 case USB_CHG_STATE_UNDEFINED:
541 mutex_lock(&rk_phy->mutex);
542 /* put the controller in non-driving mode */
543 val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL, RK3288_UOC0_CON2_SOFT_CON_SEL);
544 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
545 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING,
546 RK3288_UOC0_CON3_UTMI_SUSPENDN | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
547 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
548 /* Start DCD processing stage 1 */
549 val = HIWORD_UPDATE(RK3288_UOC0_CON2_DCDENB, RK3288_UOC0_CON2_DCDENB);
550 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
551 rk_phy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
552 dcd_retries = 0;
553 primary_retries = 0;
554 delay = CHG_DCD_POLL_TIME;
555 break;
556 case USB_CHG_STATE_DCD_DONE:
557 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
558 vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
559
560 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB);
561 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
562 if (vout) {
563 /* Voltage Source on DM, Probe on DP */
564 val =
565 HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB | RK3288_UOC0_CON2_CHRGSEL,
566 RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB | RK3288_UOC0_CON2_CHRGSEL);
567 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
568 delay = CHG_SECONDARY_DET_TIME;
569 rk_phy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
570 } else {
571 if (dcd_retries == CHG_DCD_MAX_RETRIES) {
572 /* floating charger found */
573 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
574 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
575 delay = 0;
576 } else if (primary_retries < PHY_ROCKCHIP_USB_PRIMARY_RETRIES) {
577 primary_retries++;
578 goto vdpsrc;
579 } else {
580 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB;
581 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
582 delay = 0;
583 }
584 }
585 break;
586 case USB_CHG_STATE_WAIT_FOR_DCD:
587 /* get data contact detection status */
588 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
589 fsvplus = (val & RK3288_SOC_STATUS19_FSVPLUS) ? true : false;
590 tmout = ++dcd_retries == CHG_DCD_MAX_RETRIES;
591 /* stage 2 */
592 if (!fsvplus || tmout) {
593 vdpsrc:
594 /* stage 4 */
595 /* Turn off DCD circuitry */
596 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_DCDENB);
597 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
598 /* Voltage Source on DP, Probe on DM */
599 val =
600 HIWORD_UPDATE(RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB,
601 RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB | RK3288_UOC0_CON2_CHRGSEL);
602 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
603 delay = CHG_PRIMARY_DET_TIME;
604 rk_phy->chg_state = USB_CHG_STATE_DCD_DONE;
605 } else {
606 /* stage 3 */
607 delay = CHG_DCD_POLL_TIME;
608 }
609 break;
610 case USB_CHG_STATE_PRIMARY_DONE:
611 regmap_read(rk_phy->base->reg_base, RK3288_SOC_STATUS19, &val);
612 vout = (val & RK3288_SOC_STATUS19_CHGDET) ? true : false;
613
614 /* Turn off voltage source */
615 val =
616 HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB | RK3288_UOC0_CON2_VDATDETENB | RK3288_UOC0_CON2_CHRGSEL);
617 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
618 if (vout) {
619 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
620 } else {
621 rk_phy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
622 }
623 fallthrough;
624 case USB_CHG_STATE_SECONDARY_DONE:
625 rk_phy->chg_state = USB_CHG_STATE_DETECTED;
626 fallthrough;
627 case USB_CHG_STATE_DETECTED:
628 /* put the controller in normal mode */
629 val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_SOFT_CON_SEL);
630 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON2, val);
631 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_SUSPENDN,
632 RK3288_UOC0_CON3_UTMI_SUSPENDN | RK3288_UOC0_CON3_UTMI_OPMODE_MASK);
633 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val);
634 mutex_unlock(&rk_phy->mutex);
635 rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
636 dev_info(&rk_phy->phy->dev, "charger = %s\n", chg_to_string(rk_phy->chg_type));
637 return;
638 default:
639 mutex_unlock(&rk_phy->mutex);
640 return;
641 }
642
643 /*
644 * Hold the mutex lock during the whole charger
645 * detection stage, and release it after detect
646 * the charger type.
647 */
648 schedule_delayed_work(&rk_phy->chg_work, delay);
649 }
650
rk3288_usb_phy_bvalid_irq(int irq,void * data)651 static irqreturn_t rk3288_usb_phy_bvalid_irq(int irq, void *data)
652 {
653 struct rockchip_usb_phy *rk_phy = data;
654 int ret;
655 unsigned int val;
656
657 ret = regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
658 if (ret < 0 || !(val & RK3288_UOC0_CON4_BVALID_IRQ_PD)) {
659 return IRQ_NONE;
660 }
661
662 mutex_lock(&rk_phy->mutex);
663
664 /* clear bvalid detect irq pending status */
665 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_PD, RK3288_UOC0_CON4_BVALID_IRQ_PD);
666 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON4, val);
667
668 mutex_unlock(&rk_phy->mutex);
669
670 if (rk_phy->uart_enabled) {
671 goto out;
672 }
673
674 cancel_delayed_work_sync(&rk_phy->otg_sm_work);
675 rk3288_usb_phy_otg_sm_work(&rk_phy->otg_sm_work.work);
676 out:
677 return IRQ_HANDLED;
678 }
679
rk3288_usb_phy_probe_init(struct rockchip_usb_phy * rk_phy)680 static int rk3288_usb_phy_probe_init(struct rockchip_usb_phy *rk_phy)
681 {
682 int ret = 0;
683 unsigned int val;
684
685 if (rk_phy->reg_offset == 0x320) {
686 /* Enable Bvalid interrupt and charge detection */
687 ops.init = rk3288_usb_phy_init;
688 ops.exit = rk3288_usb_phy_exit;
689 rk_phy->bvalid_irq = of_irq_get_byname(rk_phy->np, "otg-bvalid");
690 regmap_read(rk_phy->base->reg_base, RK3288_UOC0_CON4, &val);
691 if (rk_phy->bvalid_irq <= 0) {
692 dev_err(&rk_phy->phy->dev, "no vbus valid irq provided\n");
693 ret = -EINVAL;
694 goto out;
695 }
696
697 ret = devm_request_threaded_irq(rk_phy->base->dev, rk_phy->bvalid_irq, NULL, rk3288_usb_phy_bvalid_irq,
698 IRQF_ONESHOT, "rockchip_usb_phy_bvalid", rk_phy);
699 if (ret) {
700 dev_err(&rk_phy->phy->dev, "failed to request otg-bvalid irq handle\n");
701 goto out;
702 }
703
704 rk_phy->chg_state = USB_CHG_STATE_UNDEFINED;
705 wake_lock_init(&rk_phy->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
706 INIT_DELAYED_WORK(&rk_phy->chg_work, rk3288_chg_detect_work);
707 INIT_DELAYED_WORK(&rk_phy->otg_sm_work, rk3288_usb_phy_otg_sm_work);
708
709 rk_phy->mode = of_usb_get_dr_mode_by_phy(rk_phy->np, -1);
710 if (rk_phy->mode == USB_DR_MODE_OTG || rk_phy->mode == USB_DR_MODE_UNKNOWN) {
711 ret = sysfs_create_group(&rk_phy->phy->dev.kobj, &usb2_phy_attr_group);
712 if (ret) {
713 dev_err(&rk_phy->phy->dev, "Cannot create sysfs group\n");
714 goto out;
715 }
716 }
717 } else if (rk_phy->reg_offset == 0x334) {
718 /*
719 * Setting the COMMONONN to 1'b0 for EHCI PHY on RK3288 SoC.
720 *
721 * EHCI (auto) suspend causes the corresponding usb-phy into
722 * suspend mode which would power down the inner PLL blocks in
723 * usb-phy if the COMMONONN is set to 1'b1. The PLL output
724 * clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
725 * and so on, these clocks are not only supplied for EHCI and
726 * OHCI, but also supplied for GPU and other external modules,
727 * so setting COMMONONN to 1'b0 to keep the inner PLL blocks in
728 * usb-phy always powered.
729 */
730 regmap_write(rk_phy->base->reg_base, rk_phy->reg_offset, BIT(PHY_ROCKCHIP_USB_BIT));
731 }
732 out:
733 return ret;
734 }
735
rockchip_usb_phy_init(struct rockchip_usb_phy_base * base,struct device_node * child)736 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base, struct device_node *child)
737 {
738 struct device_node *np = base->dev->of_node;
739 struct rockchip_usb_phy *rk_phy;
740 unsigned int reg_offset;
741 const char *clk_name;
742 struct clk_init_data init = {};
743 int err, i;
744
745 rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
746 if (!rk_phy) {
747 return -ENOMEM;
748 }
749
750 rk_phy->base = base;
751 rk_phy->np = child;
752 mutex_init(&rk_phy->mutex);
753
754 if (of_property_read_u32(child, "reg", ®_offset)) {
755 dev_err(base->dev, "missing reg property in node %pOFn\n", child);
756 return -EINVAL;
757 }
758
759 rk_phy->reset = of_reset_control_get(child, "phy-reset");
760 if (IS_ERR(rk_phy->reset)) {
761 rk_phy->reset = NULL;
762 }
763
764 rk_phy->reg_offset = reg_offset;
765
766 rk_phy->clk = of_clk_get_by_name(child, "phyclk");
767 if (IS_ERR(rk_phy->clk)) {
768 rk_phy->clk = NULL;
769 }
770
771 i = 0;
772 init.name = NULL;
773 while (base->pdata->phys[i].reg) {
774 if (base->pdata->phys[i].reg == reg_offset) {
775 init.name = base->pdata->phys[i].pll_name;
776 break;
777 }
778 i++;
779 }
780
781 if (!init.name) {
782 dev_err(base->dev, "phy data not found\n");
783 return -EINVAL;
784 }
785
786 if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
787 dev_dbg(base->dev, "phy%d used as uart output\n", i);
788 rk_phy->uart_enabled = true;
789 } else {
790 if (rk_phy->clk) {
791 clk_name = __clk_get_name(rk_phy->clk);
792 init.flags = 0;
793 init.parent_names = &clk_name;
794 init.num_parents = 1;
795 } else {
796 init.flags = 0;
797 init.parent_names = NULL;
798 init.num_parents = 0;
799 }
800
801 init.ops = &rockchip_usb_phy480m_ops;
802 rk_phy->clk480m_hw.init = &init;
803
804 rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
805 if (IS_ERR(rk_phy->clk480m)) {
806 err = PTR_ERR(rk_phy->clk480m);
807 goto err_clk;
808 }
809
810 err = of_clk_add_provider(child, of_clk_src_simple_get, rk_phy->clk480m);
811 if (err < 0) {
812 goto err_clk_prov;
813 }
814 }
815
816 err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action, rk_phy);
817 if (err) {
818 return err;
819 }
820
821 rk_phy->phy = devm_phy_create(base->dev, child, &ops);
822 if (IS_ERR(rk_phy->phy)) {
823 dev_err(base->dev, "failed to create PHY\n");
824 return PTR_ERR(rk_phy->phy);
825 }
826 phy_set_drvdata(rk_phy->phy, rk_phy);
827
828 if (of_device_is_compatible(np, "rockchip,rk3288-usb-phy")) {
829 err = rk3288_usb_phy_probe_init(rk_phy);
830 if (err) {
831 return err;
832 }
833 }
834
835 rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus");
836 if (IS_ERR(rk_phy->vbus)) {
837 if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER) {
838 return PTR_ERR(rk_phy->vbus);
839 }
840 rk_phy->vbus = NULL;
841 }
842
843 /*
844 * When acting as uart-pipe, just keep clock on otherwise
845 * only power up usb phy when it use, so disable it when init
846 */
847 if (rk_phy->uart_enabled) {
848 return clk_prepare_enable(rk_phy->clk);
849 } else {
850 return rockchip_usb_phy_power(rk_phy, 1);
851 }
852
853 err_clk_prov:
854 if (!rk_phy->uart_enabled) {
855 clk_unregister(rk_phy->clk480m);
856 }
857 err_clk:
858 if (rk_phy->clk) {
859 clk_put(rk_phy->clk);
860 }
861 return err;
862 }
863
864 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
865 .phys = (struct rockchip_usb_phys[]) {
866 {.reg = 0x17c, .pll_name = "sclk_otgphy0_480m"},
867 {.reg = 0x188, .pll_name = "sclk_otgphy1_480m"},
868 {}},
869 };
870
rockchip_init_usb_uart_common(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)871 static int __init rockchip_init_usb_uart_common(struct regmap *grf, const struct rockchip_usb_phy_pdata *pdata)
872 {
873 int regoffs = pdata->phys[pdata->usb_uart_phy].reg;
874 int ret;
875 u32 val;
876
877 /*
878 * COMMON_ON and DISABLE settings are described in the TRM,
879 * but were not present in the original code.
880 * Also disable the analog phy components to save power.
881 */
882 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N | UOC_CON0_DISABLE | UOC_CON0_SIDDQ,
883 UOC_CON0_COMMON_ON_N | UOC_CON0_DISABLE | UOC_CON0_SIDDQ);
884 ret = regmap_write(grf, regoffs + UOC_CON0, val);
885 if (ret) {
886 return ret;
887 }
888
889 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, UOC_CON2_SOFT_CON_SEL);
890 ret = regmap_write(grf, regoffs + UOC_CON2, val);
891 if (ret) {
892 return ret;
893 }
894
895 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING | UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC |
896 UOC_CON3_UTMI_TERMSEL_FULLSPEED,
897 UOC_CON3_UTMI_SUSPENDN | UOC_CON3_UTMI_OPMODE_MASK | UOC_CON3_UTMI_XCVRSEELCT_MASK |
898 UOC_CON3_UTMI_TERMSEL_FULLSPEED);
899 ret = regmap_write(grf, UOC_CON3, val);
900 if (ret) {
901 return ret;
902 }
903
904 return 0;
905 }
906
907 #define RK3188_UOC0_CON0 0x10c
908 #define RK3188_UOC0_CON0_BYPASSSEL BIT(9)
909 #define RK3188_UOC0_CON0_BYPASSDMEN BIT(8)
910
911 /*
912 * Enable the bypass of uart2 data through the otg usb phy.
913 * See description of rk3288-variant for details.
914 */
rk3188_init_usb_uart(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)915 static int __init rk3188_init_usb_uart(struct regmap *grf, const struct rockchip_usb_phy_pdata *pdata)
916 {
917 u32 val;
918 int ret;
919
920 ret = rockchip_init_usb_uart_common(grf, pdata);
921 if (ret) {
922 return ret;
923 }
924
925 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL | RK3188_UOC0_CON0_BYPASSDMEN,
926 RK3188_UOC0_CON0_BYPASSSEL | RK3188_UOC0_CON0_BYPASSDMEN);
927 ret = regmap_write(grf, RK3188_UOC0_CON0, val);
928 if (ret) {
929 return ret;
930 }
931
932 return 0;
933 }
934
935 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
936 .phys = (struct rockchip_usb_phys[]) {
937 {.reg = 0x10c, .pll_name = "sclk_otgphy0_480m"},
938 {.reg = 0x11c, .pll_name = "sclk_otgphy1_480m"},
939 {}},
940 .init_usb_uart = rk3188_init_usb_uart,
941 .usb_uart_phy = 0,
942 };
943
944 /*
945 * Enable the bypass of uart2 data through the otg usb phy.
946 * Original description in the TRM.
947 * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
948 * 2. Disable the pull-up resistance on the D+ line by setting
949 * OPMODE0[1:0] to 2’b01.
950 * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
951 * mode, set COMMONONN to 1’b1.
952 * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
953 * 5. Set BYPASSSEL0 to 1’b1.
954 * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
955 * To receive data, monitor FSVPLUS0.
956 *
957 * The actual code in the vendor kernel does some things differently.
958 */
rk3288_init_usb_uart(struct regmap * grf,const struct rockchip_usb_phy_pdata * pdata)959 static int __init rk3288_init_usb_uart(struct regmap *grf, const struct rockchip_usb_phy_pdata *pdata)
960 {
961 u32 val;
962 int ret;
963
964 ret = rockchip_init_usb_uart_common(grf, pdata);
965 if (ret) {
966 return ret;
967 }
968
969 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL | RK3288_UOC0_CON3_BYPASSDMEN,
970 RK3288_UOC0_CON3_BYPASSSEL | RK3288_UOC0_CON3_BYPASSDMEN);
971 ret = regmap_write(grf, RK3288_UOC0_CON3, val);
972 if (ret) {
973 return ret;
974 }
975
976 return 0;
977 }
978
979 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
980 .phys = (struct rockchip_usb_phys[]) {
981 {.reg = 0x320, .pll_name = "sclk_otgphy0_480m"},
982 {.reg = 0x334, .pll_name = "sclk_otgphy1_480m"},
983 {.reg = 0x348, .pll_name = "sclk_otgphy2_480m"},
984 {}},
985 .init_usb_uart = rk3288_init_usb_uart,
986 .usb_uart_phy = 0,
987 };
988
rockchip_usb_phy_probe(struct platform_device * pdev)989 static int rockchip_usb_phy_probe(struct platform_device *pdev)
990 {
991 struct device *dev = &pdev->dev;
992 struct rockchip_usb_phy_base *phy_base;
993 struct phy_provider *phy_provider;
994 const struct of_device_id *match;
995 struct device_node *child;
996 int err;
997
998 phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
999 if (!phy_base) {
1000 return -ENOMEM;
1001 }
1002
1003 match = of_match_device(dev->driver->of_match_table, dev);
1004 if (!match || !match->data) {
1005 dev_err(dev, "missing phy data\n");
1006 return -EINVAL;
1007 }
1008
1009 phy_base->pdata = match->data;
1010
1011 phy_base->dev = dev;
1012 phy_base->reg_base = ERR_PTR(-ENODEV);
1013 if (dev->parent && dev->parent->of_node) {
1014 phy_base->reg_base = syscon_node_to_regmap(dev->parent->of_node);
1015 }
1016 if (IS_ERR(phy_base->reg_base)) {
1017 phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
1018 }
1019 if (IS_ERR(phy_base->reg_base)) {
1020 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
1021 return PTR_ERR(phy_base->reg_base);
1022 }
1023
1024 err = rockchip_usb_phy_extcon_register(phy_base);
1025 if (err) {
1026 return err;
1027 }
1028
1029 for_each_available_child_of_node(dev->of_node, child)
1030 {
1031 err = rockchip_usb_phy_init(phy_base, child);
1032 if (err) {
1033 of_node_put(child);
1034 return err;
1035 }
1036 }
1037
1038 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1039
1040 return PTR_ERR_OR_ZERO(phy_provider);
1041 }
1042
1043 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
1044 {.compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata},
1045 {.compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata},
1046 {.compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata},
1047 {}};
1048
1049 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
1050
1051 static struct platform_driver rockchip_usb_driver = {
1052 .probe = rockchip_usb_phy_probe,
1053 .driver =
1054 {
1055 .name = "rockchip-usb-phy",
1056 .of_match_table = rockchip_usb_phy_dt_ids,
1057 },
1058 };
1059
1060 module_platform_driver(rockchip_usb_driver);
1061
1062 #ifndef MODULE
rockchip_init_usb_uart(void)1063 static int __init rockchip_init_usb_uart(void)
1064 {
1065 const struct of_device_id *match;
1066 const struct rockchip_usb_phy_pdata *data;
1067 struct device_node *np;
1068 struct regmap *grf;
1069 int ret;
1070
1071 if (!enable_usb_uart) {
1072 return 0;
1073 }
1074
1075 np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids, &match);
1076 if (!np) {
1077 pr_err("%s: failed to find usbphy node\n", __func__);
1078 return -ENOTSUPP;
1079 }
1080
1081 pr_debug("%s: using settings for %s\n", __func__, match->compatible);
1082 data = match->data;
1083
1084 if (!data->init_usb_uart) {
1085 pr_err("%s: usb-uart not available on %s\n", __func__, match->compatible);
1086 return -ENOTSUPP;
1087 }
1088
1089 grf = ERR_PTR(-ENODEV);
1090 if (np->parent) {
1091 grf = syscon_node_to_regmap(np->parent);
1092 }
1093 if (IS_ERR(grf)) {
1094 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1095 }
1096 if (IS_ERR(grf)) {
1097 pr_err("%s: Missing rockchip,grf property, %lu\n", __func__, PTR_ERR(grf));
1098 return PTR_ERR(grf);
1099 }
1100
1101 ret = data->init_usb_uart(grf, data);
1102 if (ret) {
1103 pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
1104 enable_usb_uart = 0;
1105 return ret;
1106 }
1107
1108 return 0;
1109 }
1110 early_initcall(rockchip_init_usb_uart);
1111
rockchip_usb_uart(char * buf)1112 static int __init rockchip_usb_uart(char *buf)
1113 {
1114 enable_usb_uart = true;
1115 return 0;
1116 }
1117 early_param("rockchip.usb_uart", rockchip_usb_uart);
1118 #endif
1119
1120 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
1121 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
1122 MODULE_LICENSE("GPL v2");
1123