Lines Matching +full:clear +full:- +full:bit

1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR.  On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28    CVE-2019-11135  TAA    TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
58 Because the buffers are potentially shared between Hyper-Threads cross
59 Hyper-Thread attacks are possible.
70 ----------------
87 -----------------------
96 .. list-table::
98    * - 'Vulnerable'
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
100    * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101      - The processor is vulnerable but microcode is not updated. The
107        instructions without a guarantee that they clear the CPU buffers.
114    * - 'Mitigation: Clear CPU buffers'
115      - The microcode has been updated to clear the buffers. TSX is still enabled.
116    * - 'Mitigation: TSX disabled'
117      - TSX is disabled.
118    * - 'Not affected'
119      - The CPU is not affected by this issue.
122 --------------------
146 ---------------------------------------------
157                 system it will clear CPU buffers on ring transitions. On
158                 systems which are MDS-affected and deploy MDS mitigation,
165                 CPU is not vulnerable to cross-thread TAA attacks.
193                 several previous speculation-related CVEs, and so there may be
206   tsx=on     tsx_async_abort=full         The system will use VERW to clear CPU
207                                           buffers. Cross-thread attacks are still
209   tsx=on     tsx_async_abort=full,nosmt   As above, cross-thread attacks on SMT
220 For unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU
225 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
235                                      VERW is not guaranteed to clear buffers
241 --------------------------
266 -------------------
270   - Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).