Lines Matching +full:cache +full:- +full:level

7 systems from MMU-less microcontrollers to supercomputers. The memory
52 The tables at the lowest level of the hierarchy contain physical
55 levels. The pointer to the top level page table resides in a
57 register to access the top level page table. The high bits of the
58 virtual address are used to index an entry in the top level page
59 table. That entry is then used to access the next level in the
61 that level page table. The lowest bits in the virtual address define
69 processor cycles on the address translation, CPUs maintain a cache of
78 and the third level page tables. In Linux such pages are called
80 improves TLB hit-rate and thus improves overall system performance.
87 Documentation/admin-guide/mm/hugetlbpage.rst.
94 name. See Documentation/admin-guide/mm/transhuge.rst for more details
118 Many multi-processor machines are NUMA - Non-Uniform Memory Access -
126 Documentation/admin-guide/mm/numa_memory_policy.rst.
128 Page cache
133 data is put into the `page cache` to avoid expensive disk access on
135 is placed in the page cache and eventually gets into the backing
164 because they cache the data available elsewhere, for instance, on a
167 reclaimable pages are page cache and anonymous memory.
173 reclaimed. For instance, in-memory caches of filesystem metadata can
174 be re-read from the storage device and therefore it is possible to
189 more and reaches another threshold - min watermark - an allocation