Lines Matching +full:i +full:- +full:cache +full:- +full:size
10 as CPU cache coherence, but may have different performance. For example,
21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
31 CPUs or separate memory I/O devices that can initiate memory requests.
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
82 # tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
84 |-- read_bandwidth
85 |-- read_latency
86 |-- write_bandwidth
87 `-- write_latency
99 NUMA Cache
107 higher performing memory to transparently cache access to progressively
111 hierarchy. Each increasing cache level provides higher performing
113 cache provided by the system.
115 This numbering is different than CPU caches where the cache level (ex:
116 L1, L2, L3) uses the CPU-side view where each increased level is lower
117 performing. In contrast, the memory cache level is centric to the last
118 level memory, so the higher numbered cache level corresponds to memory
121 The memory-side caches are not directly addressable by software. When
123 near memory cache if it is present. If it is not present, the system
125 cache level, or it reaches far memory.
128 to use the system. Software may optionally query the memory cache
134 When the kernel first registers a memory cache with a node, the kernel
140 a memory-side cache, or that information is not accessible to the kernel.
142 The attributes for each level of cache is provided under its cache
149 Each cache level's directory provides its attributes. For example, the
150 following shows a single cache level and the attributes available for
155 |-- index1
156 | |-- indexing
157 | |-- line_size
158 | |-- size
159 | `-- write_policy
161 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
162 for any other indexed based, multi-way associativity.
164 The "line_size" is the number of bytes accessed from the next cache
167 The "size" is the number of bytes provided by this cache level.
169 The "write_policy" will be 0 for write-back, and non-zero for
170 write-through caching.
176 - Section 5.2.27