Lines Matching full:counter

7 counters is implemented. This is controlled by the CSV modes programmed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
43   AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
44   When non-masked bits are matching corresponding AXI_ID bits then counter is
45   incremented. Perf counter is incremented if::
75   extension of AXI ID filter. One improvement is that counter 1-3 has their own
77   improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
80   Filter is defined with 2 configuration registers per counter 1-3.
81   --Counter N MASK COMP register - including AXI_ID and AXI_MASKING.
82   --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.