Lines Matching +full:counter +full:- +full:0

7 counters is implemented. This is controlled by the CSV modes programmed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
23     .. code-block:: bash
25         perf stat -a -e imx8_ddr0/cycles/ cmd
26         perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
33 un-supported, and value 1 for supported.
35 * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0).
37   --AXI_ID defines AxID matching value.
38   --AXI_MASKING defines which bits of AxID are meaningful for the matching.
40       - 0: corresponding bit is masked.
41       - 1: corresponding bit is not masked, i.e. used to do the matching.
43   AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
44   When non-masked bits are matching corresponding AXI_ID bits then counter is
45   incremented. Perf counter is incremented if::
49   This filter doesn't support filter different AXI ID for axid-read and axid-write
52   .. code-block:: bash
54       perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
55       perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
63   .. code-block:: bash
65         perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
67 * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0).
72 * With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1).
75   extension of AXI ID filter. One improvement is that counter 1-3 has their own
77   improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
80   Filter is defined with 2 configuration registers per counter 1-3.
81   --Counter N MASK COMP register - including AXI_ID and AXI_MASKING.
82   --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
84       - 0: address channel
85       - 1: data channel
88   which should be 0.
90   .. code-block:: bash
92       perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd
93       perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd