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16 ``intel_idle`` is a part of the
19 Nehalem and later generations of Intel processors, but the level of support for
27 logical CPU executing it is idle and so it may be possible to put some of the
29 arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the
30 first of which, referred to as a *hint*, can be used by the processor to
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
53 depend on the configuration of the platform.
55 In order to create a list of available idle states required by the ``CPUIdle``
58 ``intel_idle`` can use two sources of information: static tables of idle states
60 of the system.  The former are always used if the processor model at hand is
68 If the ACPI tables are going to be used for building the list of available idle
69 states, ``intel_idle`` first looks for a ``_CST`` object under one of the ACPI
71 [2]_ for the description of ``_CST`` and its output package).  Because the
72 ``CPUIdle`` subsystem expects that the list of idle states supplied by the
73 driver will be suitable for all of the CPUs handled by it and ``intel_idle`` is
74 registered as the ``CPUIdle`` driver for all of the CPUs in the system, the
76 state description and such that all of the idle states included in its return
77 package are of the FFH (Functional Fixed Hardware) type, which means that the
79 enter one of them.  The return package of that ``_CST`` is then assumed to be
80 applicable to all of the other CPUs in the system and the idle state
81 descriptions extracted from it are stored in a preliminary list of idle states
85 Next, the first (index 0) entry in the list of available idle states is
91 (static) table of idle state descriptions for it in the driver.  In that case,
92 the "internal" table is the primary source of information on idle states and the
93 information from it is copied to the final list of available idle states.  If
94 using the ACPI tables for the enumeration of idle states is not required
95 (depending on the processor model), all of the listed idle state are enabled by
96 default (so all of them will be taken into consideration by ``CPUIdle``
97 governors during CPU idle state selection).  Otherwise, some of the listed idle
99 preliminary list of idle states coming from the ACPI tables.  In that case user
100 space still can enable them later (on a per-CPU basis) with the help of
108 supports ``MWAIT``, the preliminary list of idle states coming from the ACPI
112 entry in the final list of idle states.  The name of the idle state represented
114 "CX_ACPI", where X is the index of that idle state in the final list (note that
115 the minimum value of X is 1, because 0 is reserved for the "polling" state), and
118 (for compatibility with the majority of the "internal" tables of idle states for
122 in the majority of cases for the processor models recognized by ``intel_idle``).
123 All of the idle states in the final list are enabled by default in this case.
131 The initialization of ``intel_idle`` starts with checking if the kernel command
132 line options forbid the use of the ``MWAIT`` instruction.  If that is the case,
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
140 driver initialization fails if the level of support is not as expected (for
141 example, if the total number of ``MWAIT`` substates returned is 0).
147 Then, ``CPUIdle`` device objects are allocated for all CPUs and the list of
149 `above <intel-idle-enumeration-of-states_>`_.
151 Finally, ``intel_idle`` is registered with the help of cpuidle_register_driver()
154 (among other things) causes the callback routine to be invoked for all of the
155 CPUs present in the system at that time (each CPU executes its own instance of
169 and ``idle=nomwait``.  If any of them is present in the kernel command line, the
170 ``MWAIT`` instruction is not allowed to be used, so the initialization of
178 of idle states supplied to the ``CPUIdle`` core during the registration of the
179 driver.  It is also the maximum number of regular (non-polling) idle states that
180 can be used by ``intel_idle``, so the enumeration of idle states is terminated
181 after finding that number of usable idle states (the other idle states that
189 working state of the system the CPU power management quality of service (PM
197 driver ignore the system's ACPI tables entirely or use them for all of the
201 The value of the ``states_off`` module parameter (0 by default) represents a
202 list of idle states to be disabled by default in the form of a bitmask.
204 Namely, the positions of the bits that are set in the ``states_off`` value are
205 the indices of idle states to be disabled by default (as reflected by the names
206 of the corresponding idle state directories in ``sysfs``, :file:`state0`,
207 :file:`state1` ... :file:`state<i>` ..., where ``<i>`` is the index of the given
230 mode to off when the CPU is in any one of the available idle states.  This may
231 help performance of a sibling CPU at the expense of a slightly higher wakeup
237 Core and Package Levels of Idle States
241 least) two levels of idle states (or C-states).  One level, referred to as
244 and it may also involve other components of the system (GPUs, memory
247 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
249 to the ``C1`` idle state), but the majority of them give it a license to put
255 ``CC3``), which happens if all of the logical CPUs (SMT siblings) in that core
257 representing a deeper idle state), and in addition to that (in the majority of
261 all of the cores have gone into the ``CC3`` state and (possibly) some additional
271 values corresponding to the majority of ``MWAIT`` hint values in the "internal"
272 tables of idle states in ``intel_idle`` reflect the properties of package
274 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
276 restrict the range of permissible idle states to the ones with core-level only