Lines Matching +full:cpu +full:- +full:core

1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``).  It is the default CPU idle time management driver for the
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
27 logical CPU executing it is idle and so it may be possible to put some of the
28 processor's functional blocks into low-power states.  That instruction takes two
29 arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
83 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
86 initialized to represent a "polling idle state" (a pseudo-idle state in which
87 the target CPU continuously fetches and executes instructions), and the
97 governors during CPU idle state selection).  Otherwise, some of the listed idle
100 space still can enable them later (on a per-CPU basis) with the help of
102 :ref:`idle-states-representation` in
103 Documentation/admin-guide/pm/cpuidle.rst).  This basically means that
110 ``CPUIdle`` core during driver registration.  For each idle state in that list,
117 C1-type idle states the exit latency value is also used as the target residency
126 .. _intel-idle-initialization:
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
144 `below <intel-idle-parameters_>`_), the idle states information provided by the
149 `above <intel-idle-enumeration-of-states_>`_.
152 as the ``CPUIdle`` driver for all CPUs in the system and a CPU online callback
155 CPUs present in the system at that time (each CPU executes its own instance of
156 the callback routine).  That routine registers a ``CPUIdle`` device for the CPU
157 running it (which enables the ``CPUIdle`` subsystem to operate that CPU) and
158 optionally performs some CPU-specific initialization actions that may be
162 .. _intel-idle-parameters:
168 options related to CPU idle time management: ``idle=poll``, ``idle=halt``,
178 of idle states supplied to the ``CPUIdle`` core during the registration of the
179 driver.  It is also the maximum number of regular (non-polling) idle states that
185 some reason to the ``CPUIdle`` core, but it does so by making them effectively
189 working state of the system the CPU power management quality of service (PM
191 even if they have been enumerated (see :ref:`cpu-pm-qos` in
192 Documentation/admin-guide/pm/cpuidle.rst).
208 idle state; see :ref:`idle-states-representation` in
209 Documentation/admin-guide/pm/cpuidle.rst).
216 The idle states disabled this way can be enabled (on a per-CPU basis) from user
221 Speculation) should be turned off when the CPU enters an idle state.
227 have a performance impact on its sibling CPU.  The IBRS mode will be turned off
228 by default when the CPU enters into a deep idle state, but not in some
230 mode to off when the CPU is in any one of the available idle states.  This may
231 help performance of a sibling CPU at the expense of a slightly higher wakeup
232 latency for the idle CPU.
235 .. _intel-idle-core-and-package-idle-states:
237 Core and Package Levels of Idle States
241 least) two levels of idle states (or C-states).  One level, referred to as
242 "core C-states", covers individual cores in the processor, whereas the other
243 level, referred to as "package C-states", covers the entire processor package
247 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
250 the target core (i.e. the core containing the logical CPU executing ``MWAIT``
251 with the given hint value) into a specific core C-state and then (if possible)
252 to enter a specific package C-state at the deeper level.  For example, the
254 put the target core into the low-power state referred to as "core ``C3``" (or
255 ``CC3``), which happens if all of the logical CPUs (SMT siblings) in that core
259 including some non-CPU components such as a GPU or a memory controller) into the
260 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
263 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
266 As a rule, there is no simple way to make the processor use core C-states only
267 if the conditions for entering the corresponding package C-states are met, so
268 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
270 enter a package C-state.  [That is why the exit latency and target residency
273 C-states.]  If using package C-states is not desirable at all, either
274 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
275 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
276 restrict the range of permissible idle states to the ones with core-level only
283 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
284 …www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develo…