Lines Matching +full:default +full:- +full:state

1 .. SPDX-License-Identifier: GPL-2.0
18 (``CPUIdle``).  It is the default CPU idle time management driver for the
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states.  That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
76 state description and such that all of the idle states included in its return
80 applicable to all of the other CPUs in the system and the idle state
83 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
86 initialized to represent a "polling idle state" (a pseudo-idle state in which
88 subsequent (real) idle state entries are populated as follows.
91 (static) table of idle state descriptions for it in the driver.  In that case,
95 (depending on the processor model), all of the listed idle state are enabled by
96 default (so all of them will be taken into consideration by ``CPUIdle``
97 governors during CPU idle state selection).  Otherwise, some of the listed idle
98 states may not be enabled by default if there are no matching entries in the
100 space still can enable them later (on a per-CPU basis) with the help of
101 the ``disable`` idle state attribute in ``sysfs`` (see
102 :ref:`idle-states-representation` in
103 Documentation/admin-guide/pm/cpuidle.rst).  This basically means that
104 the idle states "known" to the driver may not be enabled by default if they have
110 ``CPUIdle`` core during driver registration.  For each idle state in that list,
112 entry in the final list of idle states.  The name of the idle state represented
113 by it (to be returned by the ``name`` idle state attribute in ``sysfs``) is
114 "CX_ACPI", where X is the index of that idle state in the final list (note that
115 the minimum value of X is 1, because 0 is reserved for the "polling" state), and
117 C1-type idle states the exit latency value is also used as the target residency
120 state types (C2 and C3) the target residency value is 3 times the exit latency
123 All of the idle states in the final list are enabled by default in this case.
126 .. _intel-idle-initialization:
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
144 `below <intel-idle-parameters_>`_), the idle states information provided by the
149 `above <intel-idle-enumeration-of-states_>`_.
158 optionally performs some CPU-specific initialization actions that may be
162 .. _intel-idle-parameters:
177 The ``max_cstate`` parameter value is the maximum idle state index in the list
179 driver.  It is also the maximum number of regular (non-polling) idle states that
189 working state of the system the CPU power management quality of service (PM
191 even if they have been enumerated (see :ref:`cpu-pm-qos` in
192 Documentation/admin-guide/pm/cpuidle.rst).
198 recognized processor models, respectively (they both are unset by default and
201 The value of the ``states_off`` module parameter (0 by default) represents a
202 list of idle states to be disabled by default in the form of a bitmask.
205 the indices of idle states to be disabled by default (as reflected by the names
206 of the corresponding idle state directories in ``sysfs``, :file:`state0`,
207 :file:`state1` ... :file:`state<i>` ..., where ``<i>`` is the index of the given
208 idle state; see :ref:`idle-states-representation` in
209 Documentation/admin-guide/pm/cpuidle.rst).
212 states 0 and 1 by default, and if it is equal to 8, idle state 3 will be
213 disabled by default and so on (bit positions beyond the maximum idle state index
216 The idle states disabled this way can be enabled (on a per-CPU basis) from user
221 Speculation) should be turned off when the CPU enters an idle state.
226 security vulnerabilities by default.  Leaving the IBRS mode on while idling may
228 by default when the CPU enters into a deep idle state, but not in some
235 .. _intel-idle-core-and-package-idle-states:
241 least) two levels of idle states (or C-states).  One level, referred to as
242 "core C-states", covers individual cores in the processor, whereas the other
243 level, referred to as "package C-states", covers the entire processor package
247 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
249 to the ``C1`` idle state), but the majority of them give it a license to put
251 with the given hint value) into a specific core C-state and then (if possible)
252 to enter a specific package C-state at the deeper level.  For example, the
253 ``MWAIT`` hint value representing the ``C3`` idle state allows the processor to
254 put the target core into the low-power state referred to as "core ``C3``" (or
257 representing a deeper idle state), and in addition to that (in the majority of
259 including some non-CPU components such as a GPU or a memory controller) into the
260 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
261 all of the cores have gone into the ``CC3`` state and (possibly) some additional
263 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
266 As a rule, there is no simple way to make the processor use core C-states only
267 if the conditions for entering the corresponding package C-states are met, so
268 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
270 enter a package C-state.  [That is why the exit latency and target residency
273 C-states.]  If using package C-states is not desirable at all, either
274 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
275 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
276 restrict the range of permissible idle states to the ones with core-level only
283 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
284 …www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develo…