Lines Matching +full:entry +full:- +full:latency +full:- +full:us
1 .. SPDX-License-Identifier: GPL-2.0
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
83 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
85 Next, the first (index 0) entry in the list of available idle states is
86 initialized to represent a "polling idle state" (a pseudo-idle state in which
100 space still can enable them later (on a per-CPU basis) with the help of
102 :ref:`idle-states-representation` in
103 Documentation/admin-guide/pm/cpuidle.rst). This basically means that
111 the description, ``MWAIT`` hint and exit latency are copied to the corresponding
112 entry in the final list of idle states. The name of the idle state represented
116 its target residency is based on the exit latency value. Specifically, for
117 C1-type idle states the exit latency value is also used as the target residency
120 state types (C2 and C3) the target residency value is 3 times the exit latency
121 (again, that is because it reflects the target residency to exit latency ratio
126 .. _intel-idle-initialization:
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
144 `below <intel-idle-parameters_>`_), the idle states information provided by the
149 `above <intel-idle-enumeration-of-states_>`_.
158 optionally performs some CPU-specific initialization actions that may be
162 .. _intel-idle-parameters:
179 driver. It is also the maximum number of regular (non-polling) idle states that
191 even if they have been enumerated (see :ref:`cpu-pm-qos` in
192 Documentation/admin-guide/pm/cpuidle.rst).
208 idle state; see :ref:`idle-states-representation` in
209 Documentation/admin-guide/pm/cpuidle.rst).
216 The idle states disabled this way can be enabled (on a per-CPU basis) from user
232 latency for the idle CPU.
235 .. _intel-idle-core-and-package-idle-states:
241 least) two levels of idle states (or C-states). One level, referred to as
242 "core C-states", covers individual cores in the processor, whereas the other
243 level, referred to as "package C-states", covers the entire processor package
247 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
251 with the given hint value) into a specific core C-state and then (if possible)
252 to enter a specific package C-state at the deeper level. For example, the
254 put the target core into the low-power state referred to as "core ``C3``" (or
259 including some non-CPU components such as a GPU or a memory controller) into the
260 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
263 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
266 As a rule, there is no simple way to make the processor use core C-states only
267 if the conditions for entering the corresponding package C-states are met, so
268 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
270 enter a package C-state. [That is why the exit latency and target residency
273 C-states.] If using package C-states is not desirable at all, either
274 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
275 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
276 restrict the range of permissible idle states to the ones with core-level only
283 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
284 …https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-softwar…