Lines Matching +full:per +full:- +full:processor

1 .. SPDX-License-Identifier: GPL-2.0
20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states.  That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
48 reconfigure itself in a certain way in order to save energy.  The processor
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
52 processor) corresponding to them depends on the processor model and it may also
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
59 for different processor models included in the driver itself and the ACPI tables
60 of the system.  The former are always used if the processor model at hand is
62 the given processor model (which is the case for all server processor models
63 recognized by ``intel_idle``) or if the processor model is not recognized.
65 tables with any processor model recognized by it; see
66 `below <intel-idle-parameters_>`_.]
78 ``MWAIT`` instruction is expected to be used to tell the processor that it can
83 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
86 initialized to represent a "polling idle state" (a pseudo-idle state in which
90 If the processor model at hand is recognized by ``intel_idle``, there is a
95 (depending on the processor model), all of the listed idle state are enabled by
100 space still can enable them later (on a per-CPU basis) with the help of
102 :ref:`idle-states-representation` in
103 Documentation/admin-guide/pm/cpuidle.rst).  This basically means that
107 If the given processor model is not recognized by ``intel_idle``, but it
117 C1-type idle states the exit latency value is also used as the target residency
119 various processor models recognized by ``intel_idle``) and for the other idle
122 in the majority of cases for the processor models recognized by ``intel_idle``).
126 .. _intel-idle-initialization:
135 The next step is to check whether or not the processor model is known to the
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
139 the ``MWAIT`` support in the processor is enumerated through ``CPUID`` and the
144 `below <intel-idle-parameters_>`_), the idle states information provided by the
149 `above <intel-idle-enumeration-of-states_>`_.
158 optionally performs some CPU-specific initialization actions that may be
159 required for the given processor model.
162 .. _intel-idle-parameters:
179 driver.  It is also the maximum number of regular (non-polling) idle states that
191 even if they have been enumerated (see :ref:`cpu-pm-qos` in
192 Documentation/admin-guide/pm/cpuidle.rst).
198 recognized processor models, respectively (they both are unset by default and
208 idle state; see :ref:`idle-states-representation` in
209 Documentation/admin-guide/pm/cpuidle.rst).
216 The idle states disabled this way can be enabled (on a per-CPU basis) from user
235 .. _intel-idle-core-and-package-idle-states:
240 Typically, in a processor supporting the ``MWAIT`` instruction there are (at
241 least) two levels of idle states (or C-states).  One level, referred to as
242 "core C-states", covers individual cores in the processor, whereas the other
243 level, referred to as "package C-states", covers the entire processor package
247 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
251 with the given hint value) into a specific core C-state and then (if possible)
252 to enter a specific package C-state at the deeper level.  For example, the
253 ``MWAIT`` hint value representing the ``C3`` idle state allows the processor to
254 put the target core into the low-power state referred to as "core ``C3``" (or
258 cases) it gives the processor a license to put the entire package (possibly
259 including some non-CPU components such as a GPU or a memory controller) into the
260 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
263 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
266 As a rule, there is no simple way to make the processor use core C-states only
267 if the conditions for entering the corresponding package C-states are met, so
268 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
269 only (like for ``C1``) must always assume that this may cause the processor to
270 enter a package C-state.  [That is why the exit latency and target residency
273 C-states.]  If using package C-states is not desirable at all, either
274 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
275 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
276 restrict the range of permissible idle states to the ones with core-level only
283 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
284 …www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develo…