Lines Matching +full:next +full:- +full:level +full:- +full:cache
2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
57 +---------> UP ----------+
63 +--------- DOWN <--------+
77 level. A CPU in this state is not necessarily being used
92 CPUs in the cluster simultaneously modifying the state. The cluster-
93 level states are described in the "Cluster state" section.
101 ---------
103 In this algorithm, each individual core in a multi-core processor is
104 referred to as a "CPU". CPUs are assumed to be single-threaded:
111 - CPU_DOWN
112 - CPU_COMING_UP
113 - CPU_UP
114 - CPU_GOING_DOWN
120 +-----------> CPU_UP ------------+
126 +----------- CPU_DOWN <----------+
137 next state as a result of making local progress only, with no
143 power-down. On reaching this state, the CPU will typically
147 Next state:
153 a) an explicit hardware power-up operation, resulting
165 Next state:
192 Next state:
205 Next state:
214 -------------
233 - CLUSTER_DOWN
234 - CLUSTER_UP
235 - CLUSTER_GOING_DOWN
239 - INBOUND_NOT_COMING_UP
240 - INBOUND_COMING_UP
247 +==========> INBOUND_NOT_COMING_UP -------------+
250 CLUSTER_UP <----+ |
257 INBOUND_COMING_UP <----+ |
260 +=========== CLUSTER_DOWN <------------+
263 Transitions -----> can only be made by the outbound CPU, and
290 next cycle.
294 The next state in each case is notated
303 Next state:
309 a) an explicit hardware power-up operation, resulting
318 enabling of hardware coherency at the cluster level and any
319 other operations (such as cache invalidation) which are required
322 The purpose of this state is to do sufficient cluster-level
326 Next state:
329 cluster-level setup and hardware coherency complete
336 Cluster-level setup is complete and hardware coherency is
344 Next state:
354 Cluster-level setup is complete and hardware coherency is
361 Next state:
377 cluster-level coherency.
385 Next states:
398 a) an explicit hardware power-up operation,
425 Next states:
429 cluster-level setup and hardware
444 --------------------------------
446 The CPU which performs cluster tear-down operations on the outbound side
461 non-coherent.
466 Because CPUs may power up asynchronously in response to external wake-up
468 attempts to play the first man role and do the cluster-level
472 Cluster-level initialisation may involve actions such as configuring
481 ------------------------
485 The current ARM-based implementation is split between
486 arch/arm/common/mcpm_head.S (low-level inbound CPU operations) and
496 low-level power-up code in mcpm_head.S. This could
497 involve CPU-specific setup code, but in the current
503 the case of an aborted cluster power-down).
506 functions due to the extra inter-CPU coordination which
507 is needed for safe transitions at the cluster level.
510 the low-level power-up code in mcpm_head.S. This
511 typically involves platform-specific setup code,
512 provided by the platform-specific power_up_setup
520 extended by replicating the cluster-level states for the
522 rules for the intermediate (non-outermost) cluster levels.
526 --------
531 Copyright (C) 2012-2013 Linaro Limited