Lines Matching +full:linear +full:- +full:mapping +full:- +full:mode
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
91 - As of v3.17, all fields are little endian unless stated otherwise.
93 - code0/code1 are responsible for branching to stext.
95 - when booting through EFI, code0/code1 are initially skipped.
100 - Prior to v3.17, the endianness of text_offset was not specified. In
102 endianness of the kernel. Where image_size is non-zero image_size is
103 little-endian and must be respected. Where image_size is zero,
106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
111 Bit 1-2 Kernel Page size.
113 * 0 - Unspecified.
114 * 1 - 4K
115 * 2 - 16K
116 * 3 - 64K
122 accessible via the linear mapping
126 the 48-bit addressable range of physical memory
127 Bits 4-63 Reserved.
130 - When image_size is zero, a bootloader should attempt to keep as much
156 - Quiesce all DMA capable devices so that memory does not get
160 - Primary CPU general-purpose register settings:
162 - x0 = physical address of device tree blob (dtb) in system RAM.
163 - x1 = 0 (reserved for future use)
164 - x2 = 0 (reserved for future use)
165 - x3 = 0 (reserved for future use)
167 - CPU mode
171 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
174 - Caches, MMUs
190 - Architected timers
197 - Coherency
204 - System registers
212 - If EL3 is present:
214 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
216 - The value of SCR_EL3.FIQ must be the same as the one present at boot
219 - If EL3 is present and the kernel is entered at EL2:
221 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
223 For systems with a GICv3 interrupt controller to be used in v3 mode:
224 - If EL3 is present:
226 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
228 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
232 - If the kernel is entered at EL1:
234 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
235 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
237 - The DT or ACPI tables must describe a GICv3 interrupt controller.
240 compatibility (v2) mode:
242 - If EL3 is present:
246 - If the kernel is entered at EL1:
250 - The DT or ACPI tables must describe a GICv2 interrupt controller.
254 - If EL3 is present:
256 - SCR_EL3.APK (bit 16) must be initialised to 0b1
257 - SCR_EL3.API (bit 17) must be initialised to 0b1
259 - If the kernel is entered at EL1:
261 - HCR_EL2.APK (bit 40) must be initialised to 0b1
262 - HCR_EL2.API (bit 41) must be initialised to 0b1
266 - If EL3 is present:
268 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
269 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
270 - AMCNTENSET0_EL0 must be initialised to 0b1111
271 - AMCNTENSET1_EL0 must be initialised to a platform specific value
275 - If the kernel is entered at EL1:
277 - AMCNTENSET0_EL0 must be initialised to 0b1111
278 - AMCNTENSET1_EL0 must be initialised to a platform specific value
284 - If EL3 is present and the kernel is entered at EL2:
286 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
290 - If EL3 is present and the kernel is entered at EL2:
292 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
296 - If EL3 is present and the kernel is entered at EL2:
298 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
302 - If EL3 is present:
304 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
306 - If EL2 is present and the kernel is entered at EL1:
308 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
312 - if EL3 is present:
314 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
316 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
319 - If the kernel is entered at EL1 and EL2 is present:
321 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
323 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
325 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
330 - If EL3 is present:
332 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
334 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
336 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
339 - If the kernel is entered at EL1 and EL2 is present:
341 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
343 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
345 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
347 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
350 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
352 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
354 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
356 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
360 - If EL3 is present:
362 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
364 - If the kernel is entered at EL1 and EL2 is present:
366 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
370 - If EL3 is present:
372 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
374 - If the kernel is entered at EL1 and EL2 is present:
376 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
380 - If EL3 is present:
382 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
384 - If the kernel is entered at EL1 and EL2 is present:
386 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
390 - If EL3 is present:
392 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
394 - If the kernel is entered at EL1 and EL2 is present:
396 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
397 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
398 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
400 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
401 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
402 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
406 - If the kernel is entered at EL1 and EL2 is present:
408 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
412 - If EL3 is present:
414 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
416 - If the kernel is entered at EL1 and EL2 is present:
418 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
422 - If EL3 is present:
424 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
426 - If the kernel is entered at EL1 and EL2 is present:
428 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
430 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
432 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
434 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
436 The requirements described above for CPU mode, caches, MMUs, architected
446 - The primary CPU must jump directly to the first instruction of the
448 an 'enable-method' property for each cpu node. The supported
449 enable-methods are described below.
454 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
456 naturally-aligned 64-bit zero-initalised memory location.
460 device tree) polling their cpu-release-addr location, which must be
462 to reduce the overhead of the busy-loop and a sev will be issued by
464 cpu-release-addr returns a non-zero value, the CPU must jump to this
465 value. The value will be written as a single 64-bit little-endian
469 - CPUs with a "psci" enable method should remain outside of
480 - Secondary CPU general-purpose register settings
482 - x0 = 0 (reserved for future use)
483 - x1 = 0 (reserved for future use)
484 - x2 = 0 (reserved for future use)
485 - x3 = 0 (reserved for future use)