Lines Matching +full:fpga +full:- +full:bridge

27          POWER8/9             FPGA
28        +----------+        +---------+
34        +----------+        +---------+
36        |   +------+        |   PSL   |
37        |   | CAPP |<------>|         |
38        +---+------+  PCIE  +---------+
41     unit which is part of the PCIe Host Bridge (PHB). This is managed
45     The FPGA (or coherently attached device) consists of two parts.
65     - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0.
66     - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0.
123     The WED is a 64-bit parameter passed to the AFU when a context is
157 	https://github.com/ibm-capi/libcxl
162 ----
174     and return -ENOSPC.
187 -----
220                 The Work Element Descriptor (WED) is a 64-bit argument
249 ----
263     Care should be taken when accessing MMIO space. Only 32 and 64-bit
272 ----
275     (unless O_NONBLOCK is supplied). Returns -EIO in the case of an
403     FPGA accelerator. Once the image is written and verified, the
408 ----
414 -----
417     Starts and controls flashing a new FPGA image. Partial
456     described in Documentation/ABI/testing/sysfs-class-cxl
469 	                  KERNEL=="afu[0-9]*.[0-9]*s", SYMLINK="cxl/%b"