Lines Matching +full:back +full:- +full:end

18 guaranteed to either complete atomically or roll back and undo any partial
46 The 'tbegin' instruction denotes the start point, and 'tend' the end point.
49 transactional or non-transactional accesses within the system.  In this
50 example, the transaction completes as though it were normal straight-line code
59 state will roll back to that at the 'tbegin', and control will continue from
69 - Conflicts with cache lines used by other processors
70 - Signals
71 - Context switches
72 - See the ISA for full documentation of everything that will abort transactions.
109 determine the transactional state -- if so, the second ucontext in uc->uc_link
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
117 uc->uc_link->uc_mcontext.regs->msr.  The top word contains the transactional
123 Transaction-aware signal handlers can read the transactional register state
132       ucontext_t *transactional_ucp = ucp->uc_link;
135         u64 msr = ucp->uc_mcontext.regs->msr;
138         msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32;
144                            ucp->uc_mcontext.regs->nip,
145                            transactional_ucp->uc_mcontext.regs->nip);
149       fix_the_problem(ucp->dar);
153 the stack.  It's possible that the stack has moved back up after the tbegin.
158 stack pointer will be back at the tbegin but our in memory stack won't be valid
166 signal will be rolled back anyway.
168 For signals taken in non-TM or suspended mode, we use the
169 normal/non-checkpointed stack pointer.
198 GDB and ptrace are not currently TM-aware.  If one stops during a transaction,
224 transaction to be aborted and rolled back. Kernel exceptions will also
225 cause the transaction to be aborted and rolled back and the exception
253 -------------------
257 kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM
263 be a transition from TS=01 to TS=00 (ie. suspend -> non transactional)
270      MSR 29:31 <- SRR1 29:31