Lines Matching +full:1 +full:- +full:bit

1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
10 1.  prctl() Interface
11 ---------------------
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27     argument consists of two 2-bit enablement statuses and a bit for inheritance
30     Enablement status is a tri-state value each occupying 2-bit of space in
33     * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
34       enablement status on execve(). The system-wide default setting can be
43     arg: The control argument is a 5-bit value consisting of 3 parts, and
48     represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
49     enablement status of current thread, and the setting at bit[3:2] takes place
50     at next execve(). bit[4] defines the inheritance mode of the setting in
51     bit[3:2].
53         * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
61         * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
64           then the enablement status will be decided by the system-wide
67         * :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance
68           mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
71           This setting persists across changes in the system-wide default value.
84           all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is
92     next execve() call and the inheritance bit are all OR-ed together.
95     reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
103 -----------------------------------------
112     Writing the text representation of 0 or 1 to this file sets the default
117     * 1: Allow Vector code to be executed as the default for new processes.
135 ---------------------------------------------
137 As indicated by version 1.0 of the V extension [1], vector registers are
140 1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc