Lines Matching +full:compare +full:- +full:and +full:- +full:swap
25 "SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and
27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
29 when, and only when, they appear in all capitals, as shown here.
31 For brevity and consistency, this document refers to families
32 of types using a shorthand syntax and refers to several expository,
34 The range of valid values for those types and the semantics of those
38 -----
40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
70 The following byteswap functions are direction-agnostic. That is,
74 * be16: Takes an unsigned 16-bit number and converts it between
75 host byte order and big-endian
76 (`IEN137 <https://www.rfc-editor.org/ien/ien137.txt>`_) byte order.
77 * be32: Takes an unsigned 32-bit number and converts it between
78 host byte order and big-endian byte order.
79 * be64: Takes an unsigned 64-bit number and converts it between
80 host byte order and big-endian byte order.
81 * bswap16: Takes an unsigned 16-bit number in either big- or little-endian
82 format and returns the equivalent number with the same bit width but
84 * bswap32: Takes an unsigned 32-bit number in either big- or little-endian
85 format and returns the equivalent number with the same bit width but
87 * bswap64: Takes an unsigned 64-bit number in either big- or little-endian
88 format and returns the equivalent number with the same bit width but
90 * le16: Takes an unsigned 16-bit number and converts it between
91 host byte order and little-endian byte order.
92 * le32: Takes an unsigned 32-bit number and converts it between
93 host byte order and little-endian byte order.
94 * le64: Takes an unsigned 64-bit number and converts it between
95 host byte order and little-endian byte order.
98 -----------
103 To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to
106 #. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of
107 the most-significant bit of `A`.
111 Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform:
118 ------------------
123 group and MAY support additional conformance groups, where supporting a
128 that executes instructions, and tools such as compilers that generate
142 * atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_).
143 * atomic64: includes atomic32, plus 64-bit atomic operation instructions.
144 * divmul32: includes 32-bit division, multiplication, and modulo instructions.
145 * divmul64: includes divmul32, plus 64-bit division, multiplication,
146 and modulo instructions.
159 --------------------------
163 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
165 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
167 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
172 +-+-+-+-+-+-+-+-+
174 +-+-+-+-+-+-+-+-+
183 The source and destination register numbers, encoded as follows
184 on a little-endian host::
186 +-+-+-+-+-+-+-+-+
188 +-+-+-+-+-+-+-+-+
190 and as follows on a big-endian host::
192 +-+-+-+-+-+-+-+-+
194 +-+-+-+-+-+-+-+-+
197 the source register number (0-10), except where otherwise specified
198 (`64-bit immediate instructions`_ reuse this field for other purposes)
201 destination register number (0-10), unless otherwise specified
212 Note that the contents of multi-byte fields ('offset' and 'imm') are
213 stored using big-endian byte ordering on big-endian hosts and
214 little-endian byte ordering on little-endian hosts.
228 --------------------------
231 which uses two 32-bit immediate values. The 64 bits following
233 with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero.
237 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
239 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
241 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
243 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
245 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
251 The source and destination register numbers (unless otherwise
268 -------------------
277 LD 0x0 non-standard load operations `Load and store instructions`_
278 LDX 0x1 load into register operations `Load and store instructions`_
279 ST 0x2 store from immediate operations `Load and store instructions`_
280 STX 0x3 store from register operations `Load and store instructions`_
281 ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_
282 JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_
283 JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_
284 ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_
287 Arithmetic and jump instructions
290 For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and
291 ``JMP32``), the 8-bit 'opcode' field is divided into three parts::
293 +-+-+-+-+-+-+-+-+
295 +-+-+-+-+-+-+-+-+
308 K 0 use 32-bit 'imm' value as source operand
316 -----------------------
318 ``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for
322 the source operand and 'dst' refers to the value of the destination
331 SUB 0x1 0 dst -= src
336 AND 0x5 0 dst &= src
339 NEG 0x8 0 dst = -dst
346 END 0xd 0 byte swap operations (see `Byte swap instructions`_ below)
349 Underflow and overflow are allowed during arithmetic operations, meaning
350 the 64-bit or 32-bit value will wrap. If BPF program execution would
356 ``{ADD, X, ALU}``, where 'code' = ``ADD``, 'source' = ``X``, and 'class' = ``ALU``, means::
375 (``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero 'offset'.
377 Division, multiplication, and modulo operations for ``ALU`` are part
378 of the "divmul32" conformance group, and division, multiplication, and
381 The division and modulo operations support both unsigned and signed flavors.
383 For unsigned operations (``DIV`` and ``MOD``), for ``ALU``,
384 'imm' is interpreted as a 32-bit unsigned value. For ``ALU64``,
385 'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
386 interpreted as a 64-bit unsigned value.
388 For signed operations (``SDIV`` and ``SMOD``), for ``ALU``,
389 'imm' is interpreted as a 32-bit signed value. For ``ALU64``, 'imm'
390 is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
391 interpreted as a 64-bit signed value.
397 (where -13 % 3 == -1) as implemented in C, Go, etc.::
399 a % n = a - n * trunc(a / n)
402 ``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into
403 32-bit operands, and zeroes the remaining upper 32 bits.
404 ``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
405 operands into 64-bit operands. Unlike other arithmetic instructions,
424 Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
425 for 32-bit operations.
427 Byte swap instructions
428 ----------------------
430 The byte swap instructions use instruction classes of ``ALU`` and ``ALU64``
431 and a 4-bit 'code' field of ``END``.
433 The byte swap instructions operate on the destination register
434 only and do not use a separate source register or immediate value.
436 For ``ALU``, the 1-bit source operand field in the opcode is used to
438 ``ALU64``, the 1-bit source operand field in the opcode is reserved
439 and MUST be set to 0.
441 .. table:: Byte swap instructions
446 ALU LE 0 convert between host byte order and little endian
447 ALU BE 1 convert between host byte order and big endian
448 ALU64 Reserved 0 do byte swap unconditionally
451 The 'imm' field encodes the width of the swap operations. The following widths
452 are supported: 16, 32 and 64. Width 64 operations belong to the base64
453 conformance group and other swap operations belong to the base32
477 -----------------
479 ``JMP32`` uses 32-bit wide operands and indicates the base32
480 conformance group, while ``JMP`` uses 64-bit wide operands for
481 otherwise identical operations, and indicates the base64 conformance
500 …CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-loc…
509 where 'PC' denotes the program counter, and the offset to increment by
510 is in units of 64-bit instructions relative to the instruction following
513 if the next instruction is a 128-bit wide instruction.
534 ``JMP`` class permits a 16-bit jump offset specified by the 'offset'
535 field, whereas the ``JMP32`` class permits a 32-bit jump offset
536 specified by the 'imm' field. A > 16-bit conditional jump may be
537 converted to a < 16-bit conditional jump plus a 32-bit unconditional
540 All ``CALL`` and ``JA`` instructions belong to the
551 is outside the scope of this document and standardization is left for
552 future work, but use is widely deployed and more information can be
553 found in platform-specific documentation (e.g., Linux kernel documentation).
557 identifies the helper name and type. Further documentation of BTF
558 is outside the scope of this document and standardization is left for
559 future work, but use is widely deployed and more information can be
560 found in platform-specific documentation (e.g., Linux kernel documentation).
562 Program-local functions
564 Program-local functions are functions exposed by the same BPF program as the
565 caller, and are referenced by offset from the instruction following the call
567 the call instruction. An ``EXIT`` within the program-local function will
570 Load and store instructions
573 For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the
574 8-bit 'opcode' field is divided as follows::
576 +-+-+-+-+-+-+-+-+
578 +-+-+-+-+-+-+-+-+
588 IMM 0 64-bit immediate instructions `64-bit immediate instructions`_
591 MEM 3 regular load and store operations `Regular load and store operations`_
592 MEMSX 4 sign-extension load operations `Sign-extension load operations`_
615 Regular load and store operations
616 ---------------------------------
618 The ``MEM`` mode modifier is used to encode regular load and store
619 instructions that transfer data between a register and memory.
633 Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and
636 Sign-extension load operations
637 ------------------------------
639 The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load
640 instructions that transfer data between a register and memory.
646 Where '<size>' is one of: ``B``, ``H``, or ``W``, and
650 -----------------
652 Atomic operations are operations that operate on memory and can not be
659 * ``{ATOMIC, W, STX}`` for 32-bit operations, which are
661 * ``{ATOMIC, DW, STX}`` for 64-bit operations, which are
663 * 8-bit and 16-bit wide atomic operations are not supported.
676 AND 0x50 atomic and
689 In addition to the simple atomic operations, there also is a modifier and
699 CMPXCHG 0xf0 | FETCH atomic compare and exchange
702 The ``FETCH`` modifier is optional for simple atomic operations, and
713 value that was at ``dst + offset`` before the operation is zero-extended
714 and loaded back to ``R0``.
716 64-bit immediate instructions
717 -----------------------------
720 encoding defined in `Instruction encoding`_, and use the 'src_reg' field of the
727 .. table:: 64-bit immediate instructions
743 * map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)
744 * map_by_idx(imm) means to convert a 32-bit index into an address of a map
747 …ts the address of the instruction at a specified relative offset in number of (64-bit) instructions
749 * the 'dst type' can be used for verification and JIT compilation purposes
755 A map can have various semantics as defined in a separate document, and may or
762 program at load time, and 'map_by_idx(imm)' means to get the map with the given
769 the runtime and accessible by BPF programs on some platforms. The
774 -------------------------------------
778 class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a
779 mode modifier of ``ABS`` or ``IND``. The 'dst_reg' and 'offset' fields were
780 set to zero, and 'src_reg' was set to zero for ``ABS``. However, these
781 instructions are deprecated and SHOULD no longer be used. All legacy packet