Lines Matching +full:cpu +full:- +full:nr

20 on a cpu (see mm_cpumask()), one need not perform a flush
21 for this address space on that cpu.
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
36 	visible to the cpu.
46 	'mm' will be visible to the cpu.  That is, after running,
59 	modifications for the address space 'vma->vm_mm' in the range
60 	'start' to 'end-1' will be visible to the cpu.  That is, after
62 	virtual addresses in the range 'start' to 'end-1'.
78 	address space is available via vma->vm_mm.  Also, one may
79 	test (vma->vm_flags & VM_EXEC) to see if this region is
81 	split-tlb type setups).
84 	page table modification for address space 'vma->vm_mm' for
85 	user virtual address 'addr' will be visible to the cpu.  That
87 	'vma->vm_mm' for virtual address 'addr'.
93    unsigned int nr)``
97 	in the software page tables for address space "vma->vm_mm"
98 	at virtual address "address" for "nr" consecutive pages.
104 	For example, it could use this event to pre-load TLB
109 is changing an existing virtual-->physical mapping to a new value,
126 a virtual-->physical translation to exist for a virtual address
128 cpu is one such cpu with this attribute.
131 to the extent that it is necessary for a particular cpu.  Mostly,
133 indexed caches which must be flushed when virtual-->physical
167 	entries in the cache for 'vma->vm_mm' for virtual addresses in
168 	the range 'start' to 'end-1'.
184 	address space is available via vma->vm_mm.  Also, one may
185 	test (vma->vm_flags & VM_EXEC) to see if this region is
195 	'vma->vm_mm' for virtual address 'addr' which translates
218 	space for virtual addresses in the range 'start' to 'end-1'.
224 There exists another whole class of cpu cache issues which currently
229 Is your port susceptible to virtual aliasing in its D-cache?
230 Well, if your D-cache is virtually indexed, is larger in size than
234 If your D-cache has this problem, first define asm/shmparam.h SHMLBA
236 addressed D-cache (or if the size is variable, the largest possible
246 Next, you have to solve the D-cache aliasing issue for all
251 physical page into its address space, by implication the D-cache
259 	pages.  It allows a port to efficiently avoid D-cache alias
273 	If D-cache aliasing is not an issue, these two routines may
299 	flush here to handle D-cache aliasing, to make sure these kernel stores
306 	If D-cache aliasing is not an issue, this routine may simply be defined
309         There is a bit set aside in folio->flags (PG_arch_1) as "architecture
329 			that the actual flush occurs on the same CPU
330 			as did the cpu stores into the page to make it
345 	instruction cache does not snoop cpu stores, it is very