Lines Matching full:level

36 -  Level type
51 This split implementation of high-level IRQ handlers allows us to
59 and low-level hardware logic, and it also leads to unnecessary code
61 ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
69 and only need to add the chip-level specific code. The separation is
74 Each interrupt descriptor is assigned its own high-level flow handler,
75 which is normally one of the generic implementations. (This high-level
82 IRQ-flow implementation for 'level type' interrupts and add a
102 1. High-level driver API
104 2. High-level IRQ flow handlers
106 3. Chip-level hardware encapsulation
118 Whenever an interrupt triggers, the low-level architecture code calls
120 high-level IRQ handling function only uses desc->irq_data.chip
123 High-level Driver API
126 The high-level Driver API consists of following functions:
154 High-level IRQ flow handlers
222 Default Level IRQ flow handler
225 handle_level_irq provides a generic implementation for level-triggered
322 needs to implement quirks on the 'flow' level then it can do so by
323 overriding the high-level irq-flow handler.
330 the hardware level when disable_irq() is called. The interrupt is kept
334 hardware level. When an interrupt arrives while the IRQ_DISABLED flag
335 is set, then the interrupt is masked at the hardware level and the
344 Chip-level hardware encapsulation
347 The chip-level hardware descriptor structure :c:type:`irq_chip` contains all
369 handler(s) to use these basic units of low-level functionality.
379 edge/level/simple/percpu interrupts. This is not only a functional