Lines Matching +full:instruction +full:- +full:fetch

15 specific per cpu base and encode that operation in the instruction
24 Read-modify-write operations are of particular interest. Frequently
65 ------------------------------------
71 instruction via a segment register prefix.
80 results in a single instruction::
84 instead of a sequence of calculation of the address and then a fetch
94 The above results in the following single instruction (no lock prefix!)::
114 after the this_cpu instruction is executed. In general this means that
128 ------------------
144 is re-enabled this pointer is usually no longer useful since it may
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178 --------------------------------------------
200 	this_cpu_dec(ps->m);
202 	z = this_cpu_inc_return(ps->n);
212 	pp->m--;
214 	z = pp->n++;
218 ------------------------
223 that are guaranteed to be atomic and then re-enable interrupts. Doing
252 Will increment x and will not fall-back to code that disables
254 address relocation and a Read-Modify-Write operation in the same
255 instruction.
258 &this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n)
259 --------------------------------------------
272 ------------------------------
289 To access per-cpu data structure remotely, typically the per_cpu_ptr()
313 share a cache-line but the relaxed synchronization is applied to
314 only one process updating the cache-line.