Lines Matching +full:spi +full:- +full:rx +full:- +full:bus +full:- +full:width
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
27 - const: qcom,qspi-v1
38 clock-names:
40 - const: iface
41 - const: core
45 - description: AHB clock
46 - description: QSPI core clock
52 interconnect-names:
55 - const: qspi-config
56 - const: qspi-memory
58 operating-points-v2: true
60 power-domains:
64 - compatible
65 - reg
66 - interrupts
67 - clock-names
68 - clocks
73 - |
74 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #address-cells = <2>;
79 #size-cells = <2>;
81 qspi: spi@88df000 {
82 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
84 #address-cells = <1>;
85 #size-cells = <0>;
87 clock-names = "iface", "core";
92 compatible = "jedec,spi-nor";
94 spi-max-frequency = <25000000>;
95 spi-tx-bus-width = <2>;
96 spi-rx-bus-width = <2>;