Lines Matching full:min

46 Min (GP0 to CPU BW,
47      Min(SW 0 Upstream Link to RP0 BW,
48          Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) +
49          Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) +
50      Min(SW 1 Upstream Link to RP1 BW,
51          Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) +
52          Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) +
53 Min (GP1 to CPU BW,
54      Min(SW 2 Upstream Link to RP2 BW,
55          Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) +
56          Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) +
57      Min(SW 3 Upstream Link to RP3 BW,
58          Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) +
59          Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))
63 cxl_endpoint_gather_bandwidth() function. The min() of bandwidth from the
65 has a CXL switch as a parent, then min() of calculated bandwidth and the
75 If there is another switch upstream, the code takes the min() of the current
84 The next step is to take the min() of the per host bridge bandwidth and the
86 via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same